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About

I got my graduation in Electrical and Computer Engineering in the Faculty of Engineering of the University of Porto in 1985. Since then, I was admitted as a teaching assistant in the Faculty of Engineering of the University of Porto and, at the same time, I entered in the recently created INESC in Porto. In the first years I have developed work in the areas of Operational Research, Computer Graphics and Microelectronics, the topic of my final graduation project. For several years I was with the group CAD & Microelectronics at INESC and more recently I joined the Center of Robotic and Autonomous Systems, where I have collaborated in the design and development of marine robotic systems, in particular high autonomy unmanned marine vehicles.

I concluded my PhD in Electrical and Computer Engineering in 1998, in the area of the design and development of custom computing systems. Presently I am Associate Professor in the Faculty of Engineering of the University of Porto, where I have been teaching in the areas of advanced digital design for integrated technologies, digital microelectronics and electric circuit analysis. My main R&D area is on the design and implementation of custom computing systems in reconfigurable digital systems, currently supported by FPGA technology (Field-Programmable Gate Arrays).

Interest
Topics
Details

Details

008
Publications

2021

A Novel Simulation Platform for Underwater Data Muling Communications Using Autonomous Underwater Vehicles

Authors
Teixeira, FB; Ferreira, BM; Moreira, N; Abreu, N; Villa, M; Loureiro, JP; Cruz, NA; Alves, JC; Ricardo, M; Campos, R;

Publication
Comput.

Abstract
Autonomous Underwater Vehicles (AUVs) are seen as a safe and cost-effective platforms for performing a myriad of underwater missions. These vehicles are equipped with multiple sensors which, combined with their long endurance, can produce large amounts of data, especially when used for video capturing. These data need to be transferred to the surface to be processed and analyzed. When considering deep sea operations, where surfacing before the end of the mission may be unpractical, the communication is limited to low bitrate acoustic communications, which make unfeasible the timely transmission of large amounts of data unfeasible. The usage of AUVs as data mules is an alternative communications solution. Data mules can be used to establish a broadband data link by combining short-range, high bitrate communications (e.g., RF and wireless optical) with a Delay Tolerant Network approach. This paper presents an enhanced version of UDMSim, a novel simulation platform for data muling communications. UDMSim is built upon a new realistic AUV Motion and Localization (AML) simulator and Network Simulator 3 (ns-3). It can simulate the position of the data mules, including localization errors, realistic position control adjustments, the received signal, the realistic throughput adjustments, and connection losses due to the fast SNR change observed underwater. The enhanced version includes a more realistic AML simulator and the antenna radiation patterns to help evaluating the design and relative placement of underwater antennas. The results obtained using UDMSim show a good match with the experimental results achieved using an underwater testbed. UDMSim is made available to the community to support easy and faster evaluation of underwater data muling oriented communications solutions and to enable offline replication of real world experiments.

2020

PSION plus : Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs

Authors
Truppel, A; Tseng, TM; Bertozzi, D; Alves, JC; Schlichtmann, U;

Publication
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

Abstract
Optical networks-on-chip (ONoCs) are a promising solution for high-performance multicore integration with better latency and bandwidth than traditional electrical NoCs. Wavelength-routed ONoCs (WRONoCs) offer yet additional performance guarantees. However, WRONoC design presents new EDA challenges which have not yet been fully addressed. So far, most topology analysis is abstract, i.e., overlooks layout concerns, while for layout the tools available perform place and route (P&R) but no topology optimization. Thus, a need arises for a novel optimization method combining both aspects of WRONoC design. In this article, such a method, PSION+, is laid out. This new procedure uses a linear programming model to optimize a WRONoC physical layout template to optimality. This template-based optimization scheme is a new idea in this area that seeks to minimize problem complexity while keeping design flexibility. A simple layout template format is introduced and explored. Finally, multiple model reduction techniques to reduce solver run-time are also presented and tested. When compared to the state-of-the-art design procedure, results show a decrease in maximum optical insertion loss of 41%.

2020

PSION+: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs

Authors
Truppel, A; Tseng, T; Bertozzi, D; Alves, JC; Schlichtmann, U;

Publication
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Abstract

2019

PSION: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs

Authors
Truppel, A; Tseng, TM; Bertozzi, D; Alves, JC; Schlichtmann, U;

Publication
PROCEEDINGS OF THE 2019 INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN (ISPD '19)

Abstract
Optical Networks-on-Chip (ONoCs) are a promising solution for high-performance multi-core integration with better latency and bandwidth than traditional Electrical NoCs. Wavelength-routed ONoCs (WRONoCs) offer yet additional performance guarantees. However, WRONoC design presents new EDA challenges which have not yet been fully addressed. So far, most topology analysis is abstract, i.e., overlooks layout concerns, while for layout the tools available perform Place & Route (P&R) but no topology optimization. Thus, a need arises for a novel optimization method combining both aspects of WRONoC design. In this paper such a method, PSION, is laid out. When compared to the state-of-the-art design procedure, results show a 1.8x reduction in maximum optical insertion loss.

2019

An Alternative SNR Computation Method for ADC Testing

Authors
Machado da Silva, JM; Carlos Alves, JC;

Publication
2019 XXXIV CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS)

Abstract
An alternative approach to compute the signal to noise ratio of analogue to digital converters based on the computation of the cross-correlation coefficient of the captured response is proposed here. It is shown, after simulation and experimental results, that this approach allows obtaining good accuracy results with the added advantages of not requiring coherent sampling and high purity sine wave stimuli.

Supervised
thesis

2021

Aerial high-resolution imagery to assess almond orchard conditions

Author
Nathalie dos Santos Guimarães

Institution
UTAD

2021

Rethinking a Deep Learning Pipeline for Images

Author
Ricardo Pereira de Magalhães Cruz

Institution
UP-FCUP

2021

Observability and Controllability in Scenario-based Integration Testing of Time-Constrained Distributed Systems

Author
Bruno Miguel Carvalhido Lima

Institution
UP-FEUP

2021

Field-Configurable GPU

Author
Pedro Rodrigues de Castro

Institution
UP-FEUP

2021

Deteção de patologia em sons cardíacos usando deep learning

Author
JOSÉ PEDRO INEZ DE MEIRA TORRES

Institution
IPP-ISEP