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About

About

I got my graduation in Electrical and Computer Engineering in the Faculty of Engineering of the University of Porto in 1985. Since then, I was admitted as a teaching assistant in the Faculty of Engineering of the University of Porto and, at the same time, I entered in the recently created INESC in Porto. In the first years I have developed work in the areas of Operational Research, Computer Graphics and Microelectronics, the topic of my final graduation project. For several years I was with the group CAD & Microelectronics at INESC and more recently I joined the Center of Robotic and Autonomous Systems, where I have collaborated in the design and development of marine robotic systems, in particular high autonomy unmanned marine vehicles.

I concluded my PhD in Electrical and Computer Engineering in 1998, in the area of the design and development of custom computing systems. Presently I am Associate Professor in the Faculty of Engineering of the University of Porto, where I have been teaching in the areas of advanced digital design for integrated technologies, digital microelectronics and electric circuit analysis. My main R&D area is on the design and implementation of custom computing systems in reconfigurable digital systems, currently supported by FPGA technology (Field-Programmable Gate Arrays).

Interest
Topics
Details

Details

006
Publications

2018

An FPGA array for cellular genetic algorithms: Application to the minimum energy broadcast problem

Authors
dos Santos, PV; Alves, JC; Ferreira, JC;

Publication
Microprocessors and Microsystems

Abstract
The genetic algorithm is a general purpose optimization metaheuristic for solving complex optimization problems. Because the algorithm usually requires a large number of iterations to evolve a population of solutions to good final solutions, it normally exhibits long execution times, especially if running on low-performance conventional processors. In this work, we present a scalable computing array to parallelize and accelerate the execution of cellular GAs (cGAs). This is a variant of genetic algorithms which can conveniently exploit the coarse-grain parallelism afforded by custom parallel processing. The proposed architecture targets Xilinx FPGAs and was implemented as an auxiliary processor of an embedded soft-core CPU (MicroBlaze). To facilitate the customization for different optimization problems, a high-level synthesis design flow is proposed where the problem-dependent operations are specified in C++ and synthesised to custom hardware, thus demanding of the programmer only minimal knowledge of low-level digital design for FPGAs. To demonstrate the efficiency of the array processor architecture and the effectiveness of the design methodology, the development of a hardware solver for the minimum energy broadcast problem in wireless ad hoc networks is employed as a use case. Implementation results for a Virtex-6 FPGA show significant speedups, especially when comparing to embedded processors used in current FPGA devices. © 2018

2017

Unmanned Maritime Systems for Search and Rescue

Authors
Matos, A; Silva, E; Almeida, J; Martins, A; Ferreira, H; Ferreira, B; Alves, J; Dias, A; Fioravanti, S; Bertin, D; Lobo, V;

Publication
Search and Rescue Robotics - From Theory to Practice

Abstract

2017

Cooperative deep water seafloor mapping with heterogeneous robotic platforms

Authors
Cruz, N; Abreu, N; Almeida, J; Almeida, R; Alves, J; Dias, A; Ferreira, B; Ferreira, H; Goncalves, C; Martins, A; Melo, J; Pinto, A; Pinto, V; Silva, A; Silva, H; Matos, A; Silva, E;

Publication
OCEANS 2017 - Anchorage

Abstract
This paper describes the PISCES system, an integrated approach for fully autonomous mapping of large areas of the ocean in deep waters. A deep water AUV will use an acoustic navigation system to compute is position with bounded error. The range limitation will be overcome by a moving baseline scheme, with the acoustic sources installed in robotic surface vessels with previously combined trajectories. In order to save power, all systems will have synchronized clocks and implement the One Way Travel Time scheme. The mapping system will be a combination of an off-the-shelf MBES with a new long range bathymetry system, with a source on a moving surface vessel and the receivers on board the AUV. The system is being prepared to participate in round one of the XPRIZE challenge. © 2017 Marine Technology Society.

2016

Strengthening marine and maritime research and technology

Authors
Silva, E; Martins, A; Dias, A; Matos, A; Olivier, A; Pinho, C; de Sa, FA; Ferreira, H; Silva, H; Alves, JC; Almeida, JM; Pessoa, L; Ricardo, M; Cruz, N; Dias, N; Monica, P; Jorge, P; Campos, R;

Publication
OCEANS 2016 MTS/IEEE Monterey, OCE 2016

Abstract
INESC TEC is strongly committed to become a center of excellence in maritime technology and, in particular, deep sea technology. The STRONGMAR project aims at creating solid and productive links in the global field of marine science and technology between INESC TEC and established leading research European institutions, capable of enhancing the scientific and technological capacity of INESC TEC and linked institutions, helping raising its staff's research profile and its recognition as a European maritime research center of excellence. The STRONGMAR project seeks complementarity to the TEC4SEA research infrastructure: on the one hand, TEC4SEA promotes the establishment of a unique infrastructure of research and technological development, and on the other, the STRONGMAR project intends to develop the scientific expertise of the research team of INESC TEC. © 2016 IEEE.

2016

Water-jet Propelled Autonomous Surface Vehicle UCAP: System Description and Control

Authors
Ferreira, BM; Matos, AC; Alves, JC;

Publication
OCEANS 2016 - SHANGHAI

Abstract
A new small-sized autonomous surface vehicle actuated by a water-jet has been developed at INESC TEC for search and rescue of victims at sea. This paper describes the vehicle main components and presents the control and guidance laws governing the motion and enabling it to perform line-following and target tracking missions. Results from field trials are presented, demonstrating the capabilities and the performances of the vehicle along with its control layer.

Supervised
thesis

2017

Physical Design Implementation and Engineering Change Order Flow

Author
Afonso Ferreira Pinto Gomes Moreira

Institution
UP-FEUP

2017

Implementação em Verilog de Codificador/Descodificador Reed-Solomon FEC.

Author
Artur Jorge Alves Antunes

Institution
UP-FEUP

2016

0

Author
Rosária Maria Afonso Rodrigues de Melo

Institution
UP-FCNA

2016

Verilog implementation of the VESA DSC compression algorithm

Author
Carlos Alberto Pereira Ferreira

Institution
UP-FEUP

2016

RTL Guidelines for Static Power Reduction

Author
Ciro de Moura Monteiro

Institution
UP-FEUP