Abstract
Optical Networks-on-Chip (ONoCs) are a promising solution for high-performance multi-core integration with better latency and bandwidth than traditional Electrical NoCs. Wavelength-routed ONoCs (WRONoCs) offer yet additional performance guarantees. However, WRONoC design presents new EDA challenges which have not yet been fully addressed. So far, most topology analysis is abstract, i.e., overlooks layout concerns, while for layout the tools available perform Place & Route (P&R) but no topology optimization. Thus, a need arises for a novel optimization method combining both aspects of WRONoC design. In this paper such a method, PSION, is laid out. When compared to the state-of-the-art design procedure, results show a 1.8x reduction in maximum optical insertion loss.

Abstract
The genetic algorithm is a general purpose optimization metaheuristic for solving complex optimization problems. Because the algorithm usually requires a large number of iterations to evolve a population of solutions to good final solutions, it normally exhibits long execution times, especially if running on low-performance conventional processors. In this work, we present a scalable computing array to parallelize and accelerate the execution of cellular GAs (cGAs). This is a variant of genetic algorithms which can conveniently exploit the coarse-grain parallelism afforded by custom parallel processing. The proposed architecture targets Xilinx FPGAs and was implemented as an auxiliary processor of an embedded soft-core CPU (MicroBlaze). To facilitate the customization for different optimization problems, a high-level synthesis design flow is proposed where the problem-dependent operations are specified in C++ and synthesised to custom hardware, thus demanding of the programmer only minimal knowledge of low-level digital design for FPGAs. To demonstrate the efficiency of the array processor architecture and the effectiveness of the design methodology, the development of a hardware solver for the minimum energy broadcast problem in wireless ad hoc networks is employed as a use case. Implementation results for a Virtex-6 FPGA show significant speedups, especially when comparing to embedded processors used in current FPGA devices. © 2018

Abstract

Abstract
This paper describes the PISCES system, an integrated approach for fully autonomous mapping of large areas of the ocean in deep waters. A deep water AUV will use an acoustic navigation system to compute is position with bounded error. The range limitation will be overcome by a moving baseline scheme, with the acoustic sources installed in robotic surface vessels with previously combined trajectories. In order to save power, all systems will have synchronized clocks and implement the One Way Travel Time scheme. The mapping system will be a combination of an off-the-shelf MBES with a new long range bathymetry system, with a source on a moving surface vessel and the receivers on board the AUV. The system is being prepared to participate in round one of the XPRIZE challenge. © 2017 Marine Technology Society.

Abstract
INESC TEC is strongly committed to become a center of excellence in maritime technology and, in particular, deep sea technology. The STRONGMAR project aims at creating solid and productive links in the global field of marine science and technology between INESC TEC and established leading research European institutions, capable of enhancing the scientific and technological capacity of INESC TEC and linked institutions, helping raising its staff's research profile and its recognition as a European maritime research center of excellence. The STRONGMAR project seeks complementarity to the TEC4SEA research infrastructure: on the one hand, TEC4SEA promotes the establishment of a unique infrastructure of research and technological development, and on the other, the STRONGMAR project intends to develop the scientific expertise of the research team of INESC TEC. © 2016 IEEE.