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Sobre
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Sobre

Licenciei-me em Engenharia Eletrotécnica e Computadores na Faculdade de Engenharia da Universidade do Porto em 1985. Desde essa data entrei na Faculdade de Engenharia como Assistente Estagiário e ao mesmo tempo no recém criado INESC do Porto, onde nos primeiros anos desenvolvi trabalho na área da Investigação Operacional, Computação Gráfica e Microeletrónica, que foi o tema do meu projeto final de curso. Durante vários anos estive integrado no grupo de CAD e Microeletrónica do INESC Porto e mais recentemente associei-me ao atual Centro de Robótica e Sistemas Autónomos onde tenho colaborado na conceção e desenvolvimento de sistemas robóticos marinhos, em particular veículos autónomos de elevada autonomia. 

Concluí o Doutoramento em Engenharia Eletrotécnica e Computadores em 1998, na área da conceção e desenvolvimento de sistemas computacionais reconfiguráveis. Atualmente sou Professor Associado na Faculdade de Engenharia da Universidade do Porto onde tenho lecionado nas áreas de projeto de sistemas digitais para tecnologias microintegradas, microeletrónica digital e circuitos elétricos. A minha área de especialização principal situa-se na conceção de sistemas computacionais dedicados e sua implementação em plataformas digitais reconfiguráveis baseados em dispositivos digitais FPGA (Field-Programmable Gate Array).

Tópicos
de interesse
Detalhes

Detalhes

007
Publicações

2019

PSION: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs

Autores
Truppel, A; Tseng, TM; Bertozzi, D; Alves, JC; Schlichtmann, U;

Publicação
PROCEEDINGS OF THE 2019 INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN (ISPD '19)

Abstract
Optical Networks-on-Chip (ONoCs) are a promising solution for high-performance multi-core integration with better latency and bandwidth than traditional Electrical NoCs. Wavelength-routed ONoCs (WRONoCs) offer yet additional performance guarantees. However, WRONoC design presents new EDA challenges which have not yet been fully addressed. So far, most topology analysis is abstract, i.e., overlooks layout concerns, while for layout the tools available perform Place & Route (P&R) but no topology optimization. Thus, a need arises for a novel optimization method combining both aspects of WRONoC design. In this paper such a method, PSION, is laid out. When compared to the state-of-the-art design procedure, results show a 1.8x reduction in maximum optical insertion loss.

2019

An Alternative SNR Computation Method for ADC Testing

Autores
Machado da Silva, JM; Carlos Alves, JC;

Publicação
2019 XXXIV CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS)

Abstract
An alternative approach to compute the signal to noise ratio of analogue to digital converters based on the computation of the cross-correlation coefficient of the captured response is proposed here. It is shown, after simulation and experimental results, that this approach allows obtaining good accuracy results with the added advantages of not requiring coherent sampling and high purity sine wave stimuli.

2018

An FPGA array for cellular genetic algorithms: Application to the minimum energy broadcast problem

Autores
dos Santos, PV; Alves, JC; Ferreira, JC;

Publicação
Microprocessors and Microsystems

Abstract
The genetic algorithm is a general purpose optimization metaheuristic for solving complex optimization problems. Because the algorithm usually requires a large number of iterations to evolve a population of solutions to good final solutions, it normally exhibits long execution times, especially if running on low-performance conventional processors. In this work, we present a scalable computing array to parallelize and accelerate the execution of cellular GAs (cGAs). This is a variant of genetic algorithms which can conveniently exploit the coarse-grain parallelism afforded by custom parallel processing. The proposed architecture targets Xilinx FPGAs and was implemented as an auxiliary processor of an embedded soft-core CPU (MicroBlaze). To facilitate the customization for different optimization problems, a high-level synthesis design flow is proposed where the problem-dependent operations are specified in C++ and synthesised to custom hardware, thus demanding of the programmer only minimal knowledge of low-level digital design for FPGAs. To demonstrate the efficiency of the array processor architecture and the effectiveness of the design methodology, the development of a hardware solver for the minimum energy broadcast problem in wireless ad hoc networks is employed as a use case. Implementation results for a Virtex-6 FPGA show significant speedups, especially when comparing to embedded processors used in current FPGA devices. © 2018

2017

Unmanned Maritime Systems for Search and Rescue

Autores
Matos, A; Silva, E; Almeida, J; Martins, A; Ferreira, H; Ferreira, B; Alves, J; Dias, A; Fioravanti, S; Bertin, D; Lobo, V;

Publicação
Search and Rescue Robotics - From Theory to Practice

Abstract

2017

Cooperative deep water seafloor mapping with heterogeneous robotic platforms

Autores
Cruz, N; Abreu, N; Almeida, J; Almeida, R; Alves, J; Dias, A; Ferreira, B; Ferreira, H; Goncalves, C; Martins, A; Melo, J; Pinto, A; Pinto, V; Silva, A; Silva, H; Matos, A; Silva, E;

Publicação
OCEANS 2017 - Anchorage

Abstract
This paper describes the PISCES system, an integrated approach for fully autonomous mapping of large areas of the ocean in deep waters. A deep water AUV will use an acoustic navigation system to compute is position with bounded error. The range limitation will be overcome by a moving baseline scheme, with the acoustic sources installed in robotic surface vessels with previously combined trajectories. In order to save power, all systems will have synchronized clocks and implement the One Way Travel Time scheme. The mapping system will be a combination of an off-the-shelf MBES with a new long range bathymetry system, with a source on a moving surface vessel and the receivers on board the AUV. The system is being prepared to participate in round one of the XPRIZE challenge. © 2017 Marine Technology Society.

Teses
supervisionadas

2019

Testes e Validação De Um Painel Digital Automóvel Usando Visão Computacional

Autor
João Pedro Alves Teixeira

Instituição
UP-FEUP

2019

Reconfigurable localization for AUVs based on Time of Arrival of encoded acoustic signals

Autor
Tiago Coelho Brandão Pinto

Instituição
UP-FEUP

2019

Acoustic system for ground truth underwater positioning in DEEC's test tank

Autor
Afonso Mateus Bonito

Instituição
UP-FEUP

2019

Store-and-forward CDC packet transmission in digital systems

Autor
Tiago Filipe Almeida Campos

Instituição
UP-FEUP

2019

Detection and Classification of Obstacles for Autonomous Vessels Using Machine Learning

Autor
António Pedro Rodrigues Pereira

Instituição
UP-FEUP