Abstract

Abstract
In this paper we address the ability of WorldFIP to cope with the real-time requirements of distributed computer-controlled systems (DCCS). Typical DCCS include process variables that must be transferred between network devices both in a periodic and sporadic (aperiodic) basis. The WorldFIP protocol is designed to support both types of traffic. WorldFIP can easily guarantee the timing requirements for the periodic traffic. However, for the aperiodic traffic more complex analysis must be made in order to guarantee its timing requirements. This paper describes work that is being carried out to extend previous relevant work, in order to include the actual schedule for the periodic traffic in the worst-case response time analysis of sporadic traffic in WorldFIP networks.

Abstract
When properly applied, statistical tools are an effective way for improving process quality. Although training on statistical process control (SPC) is increasing, unfortunately it is likely to find examples where the SPC implementation does not lead to any kind of process improvement. In fact, SPC implementation is not a simple and automatic task. Frequently the blind use of these tools causes more perplexity than value. The availability of statistical software together with the pressure for ISO 9000 registration can partially explain this situation. In this paper, the basic principles of some statistical tools are clarified, and a case-study from a ferrous castings foundry is presented, describing a situation in which the traditional inference SPC tools are not recommended. Alternatively, graphical aids are applied in order to support process management decisions.

Abstract
Fieldbus communication networks aim to interconnect sensors, actuators and controllers within process control applications. Therefore, they constitute the foundation upon which real-time distributed computer-controlled systems can be implemented. P-NET is a fieldbus communication standard, which uses a virtual token-passing medium-access-control mechanism. In this paper pre-run-time schedulability conditions for supporting real-time traffic with P-NET networks are established. Essentially, formulae to evaluate the upper bound of the end-to-end communication delay in P-NET messages are provided. Using this upper bound, a feasibility test is then provided to check the timing requirements for accessing remote process variables. This paper also shows how P-NET network segmentation can significantly reduce the end-to-end communication delays for messages with stringent timing requirements.

Abstract
In this paper we present system Ltree for propositional supervised learning. Ltree is able to define decision surfaces both orthogonal and oblique to the axes defined by the attributes of the input space. This is done combining a decision tree with a linear discriminant by means of constructive induction. At each decision node Ltree defines a new instance space by insertion of new attributes that are projections of the examples that fall at this node over the hyper-planes given by a linear discriminant function. This new instance space is propagated down through the tree. Tests based on those new attributes are oblique with respect to the original input space. Ltree is a probabilistic tree in the sense that it outputs a class probability distribution for each query example. The class probability distribution is computed at learning time, taking into account the different class distributions on the path from the root to the actual node. We have carried out experiments on twenty one benchmark datasets and compared our system with other well known decision tree systems (orthogonal and oblique) like C4.5, OC1, LMDT, and CART. On these datasets we have observed that our system has advantages in what concerns accuracy and learning times at statistically significant confidence levels.

Abstract
This paper presents a new approach to synthesize to reconfigurable hardware (HW) user-specified regions of a program, under the assumption of "virtual HW" support. The automation of this approach is supported by a compiler front-end and by an HW compiler under development. The front-end starts from the Java bytecodes and, therefore, supports any language that can be compiled to the JVM (Java Virtual Machine) model. It extracts from the bytecodes all the dependencies inside and between basic blocks. This information is stored in representation graphs more suitable to efficiently exploit the existent parallelism in the program than those typically used in high-level synthesis. From the intermediate representations the HW compiler exploits the temporal partitions at the behavior level, resolves memory access conflicts, and generates the VHDL descriptions at register-transfer level that will be mapped into the reconfigurable HW devices.