Abstract
Performance understanding and prediction are extremely important goals for guiding the application of program optimizations or in helping programmers focus their efforts when tuning their applications. In this paper we survey current approaches in performance understanding and modeling for high-performance scientific applications. We also describe a performance modeling and prediction approach that relies on the synergistic collaboration of compiler analysis, compiler-generated instrumentation (to observe relevant run-time input values) and multi-model performance modeling. A compiler analyzes the source code to derive a discrete set of parameterizable performance models. The models use run-time data to define the values of their parameters. This approach, we believe, will allow for higher performance modeling accuracy and more importantly to more precise identification of what the causes of performance problems are. © Springer-Verlag Berlin Heidelberg 2003.

Abstract
Barium metaplumbate thin films were deposited in situ by pulsed laser deposition on Si/SiO2 and Si/SiO2/Ti/Pt substrates between 400degreesC and 700degreesC. Films prepared at low temperature (less than or equal to500degreesC) over platinum were randomly oriented. For depositions made at 2x10(-2) mbar of oxygen, the films were oriented (110) for all temperatures, while at 0.1 mbar the films were oriented (110) at 500degreesC, changing to a mixed (222)/(200) orientation above 550degreesC. The conductivity of BaPbO3 reached values of 5.6x10(-5) Omega cm. The films deposited directly over silica were polycrystalline for temperatures above 500degreesC, having a strong (110) orientation only at 700degreesC. The orientation of BaPbO3 deposited either on silica or platinum, was reflected on the PZT films deposited at room temperature over BaPbO3 and crystallized by different thermal treatments. PZT capacitors made over BaPbO3 presented high values of remnant polarization (up to 44 muC/cm(2)).

Abstract
As the densities of current FPGA continue to grow it is now possible to generate System-On-a-Chip (SoC) designs where multiple computing cores are connected to various memory modules with customized topology with application specific memory access patterns. For example, Xilinx has recently introduced devices to which a paired down version of a PowerPC core can be mapped and connected to a set of internal memories. In this paper we address the problem of synthesizing and estimating the area and speed of memory interfacing for Static RAM (SRAM) and Synchronous Dynamic RAM (SDRAM) with various latency parameters and access modes. We describe a set of synthesizable and programmable memory interfaces a compiler can use to automatically generate the appropriate designs for mapping computations to FPGA-based architectures. Our preliminary results reveal that it is possible to accurately model the area and timing requirements using a linear estimation function. We have successfully integrated the proposed memory interface designs with simple image processing kernels generated using commercially available behavioral synthesis tools. © 2003 IEEE.

Abstract
Thin films of bioactive glass-ceramics have been deposited on titanium and silicon substrates by RF magnetron sputtering. The crystalline phases and the microstructure of the films have been characterized using XRD and SEM analysis; the main phases present were calcium-magnesium phosphates, enstatite and forsterite. The adhesion of the films on titanium has been examined by pull-off testing; the adhesion strength for as-deposited films was around 40 MPa, but after crystallization the strength dropped to about half this value due to the presence of cracks. Samples kept in simulated body fluid showed an apatite-like layer, suggesting that the films are bioactive.

Abstract
The utilization of adaptive replication technique for automatic elimination of synchronization bottlenecks was analyzed. Adaptive replication involves dynamic detection of contention at each object which eliminates unnecessary replication. The technique was implemented in the context of parallelizing compiler for a subset of C++. The combination of lock coarsening and adaptive replication eliminated synchronization bottlenecks and also reduced the overheads associated with the synchronization and replication processes.

Abstract
Distributed Hash Tables are the core technology on a significant share of system designs for Peer-to-Peer information sharing. Typically, a location mechanism is provided and object identifiers act as keys in the index of object locations. When introducing a search mechanism, when single words an used as keys, the key image cardinality will be driven by the word popularity and most of the present designs will be unable to load balance the index among the nodes. We present two contributions: A design that allows participating nodes to load balance the indexing of popular keys and avoid content hot-spots on single nodes; A distributed mechanism for probabilistic filtering of popular keys (with low search relevance) that paves the way for scalable full content indexing.