Abstract

Abstract
The computational requirements of full global illumination rendering are such that it is still not possible to achieve high-fidelity graphics of very complex scenes in a reasonable time on a single computer. By identifying which computations are more relevant to the desired quality of the solution, selective rendering can significantly reduce rendering times. In this paper we present a novel component-based selective rendering system in which the quality of every image, and indeed every pixel, can be controlled by means of a component regular expression (crex). The crex provides a flexible mechanism for controlling which components are rendered and in which order. It can be used as a strategy for directing the light transport within a scene and also in a progressive rendering framework. Furthermore, the crex can be combined with visual perception techniques to reduce rendering computation times without compromising the perceived visual quality. By means of a psychophysical experiment we demonstrate how the crex can be successfully used in such a perceptual rendering framework. In addition, we show how the crex's flexibility enables it to be incorporated in a predictive framework for time-constrained rendering. Copyright © 2005 by the Association for Computing Machinery, Inc.

Abstract
This paper presents recent advances in a compiler infrastructure to map algorithms described in a Java subset to FPGA-based platforms. We explain how delays and resources are estimated to guide the compiler through scheduling and temporal partitioning. The compiler supports complex analytical models to estimate resources and delays for each functional unit. The paper presents experimental results for a number of benchmarks. Those results also arrise a question when performing temporal partitioning: shall we try to group as many computational structures in the same configuration or shall we have several configurations?

Abstract
This paper presents an infrastructure to test the functionality of the specific architectures output by a high-level compiler targeting dynamically reconfigurable hardware. It results in a suitable scheme to verify the architectures generated by the compiler, each time new optimization techniques are included or changes in the compiler are performed. We believe this kind of infrastructure is important to verify, by functional simulation, further research techniques, as far as compilation to Field-Programmable Gate Array (FPGA) platforms is concerned.

Abstract
Learning from multi-relational domains has gained increasing attention over the past few years. Inductive logic programming (ILP) systems, which often rely on hill-climbing heuristics in learning first-order concepts, have been a dominating force in the area of multi-relational concept learning. However, hill-climbing heuristics are susceptible to local maxima and plateaus. In this paper, we show how we can exploit the links between objects in multi-relational data to help a first-order rule learning system direct the search by explicitly traversing these links to find paths between variables of interest. Our contributions are twofold: (i) we extend the pathfinding algorithm by Richards and Mooney [12] to make use of mode declarations, which specify the mode of call (input or output) for predicate variables, and (ii) we apply our extended path finding algorithm to saturated bottom clauses, which anchor one end of the search space, allowing us to make use of background knowledge used to build the saturated clause to further direct search. Experimental results on a medium-sized dataset show that path finding allows one to consider interesting clauses that would not easily be found by Aleph. © Springer-Verlag Berlin Heidelberg 2005.

Abstract
Inductive Logic Programming (ILP) is a popular approach for learning rules for classification tasks. An important question is how to combine the individual rules to obtain a useful classifier. In some instances, converting each learned rule into a binary feature for a Bayes net learner improves the accuracy compared to the standard decision list approach [3,4,14]. This results in a two-step process, where rules are generated in the first phase, and the classifier is learned in the second phase. We propose an algorithm that interleaves the two steps, by incrementally building a Bayes net during rule learning. Each candidate rule is introduced into the network, and scored by whether it improves the performance of the classifier. We call the algorithm SAYU for Score As You Use. We evaluate two structure learning algorithms Naïve Bayes and Tree Augmented Naïve Bayes. We test SAYU on four different datasets and see a significant improvement in two out of the four applications. Furthermore, the theories that SAYU learns tend to consist of far fewer rules than the theories in the two-step approach. © Springer-Verlag Berlin Heidelberg 2005.