Abstract
Fetal heart rate (FHR) monitoring is widely used regarding the detection of fetuses in danger of death or damage. Thirty one FHR tracings acquired in the antepartum period were clustered by compression in order to identify abnormal ones. A recently introduced approach based on algorithmic information theory was used. The new method can mine patterns in completely different areas, without domain-specific parameters to set, and does not require specific background knowledge. At the highest level the FHR tracings were clustered according to an unanticipated feature, namely the technology used in signal acquisition. At the lower levels all tracings with abnormal or suspicious patterns were clustered together, independently of the technology used.

Abstract
Coarse-grained reconfigurable array architectures are currently focus of intensive research. They have already proven performance improvements and energy savings over traditional architectures. However, coarse-grained arrays vary widely in the number and characteristics of the processing elements and routing topologies used. This work presents a flexible mapping environment for design space exploration of coarse-grained, data-driven, reconfigurable array architectures. The mapping included in the environment presented in this paper takes advantage of Java and XML technologies to enable an efficient architectural trade-off analysis. This approach does not focus on neither a specific mapping algorithm nor a specific architecture, but on an open environment where users can add their own mapping algorithms and architecture patterns. A genetic algorithm for placement is presented. A number of DSP benchmarks are used to explore a range of mesh architectures and to validate the approach. The experiments show a fast, scalable and flexible mapping environment to explore new mesh array patterns, homogeneous and heterogeneous architectures. © 2006 IEEE.

Abstract
High-performance FPGA accelerating software applications are a growing demand in fields as communications, image processing, and scientific computing among others. Moreover, as the cost per gate of FPGAs declines, embedded and high-performance systems designers are being presented with new opportunities for creating accelerated software applications using FPGA-based programmable hardware platforms. Powerful high-level language to RTL generators are now emerging. One of the promises of these tools is to allow software and systems engineers to implement algorithms quickly in a familiar language and target the design to a programmable device. The generators available today support syntaxes with different degrees of fidelity to the original language. This paper focuses on the efficient use of C to RTL generators that have a high degree of fidelity to the original C language. The objective of this project is to study some tools that starting from languages of high level as ANSI-C, and generate FPGA accelerating software applications automatically. In this paper are presented tools and partial results of the hardware generated by them.

Abstract
Public transport systems face the challenge of attracting users to fight the lost in market share, mostly due to the increasing use of private cars. Therefore, the concepts of 'quality' and 'customer' must change and the focus must be on meeting people's needs. At the same time, transport systems should be flexible enough to respond to changes in people's requirements and needs. Thus, the aim for public transport must be enhancing quality of the service. This requires a clear understanding of travel behaviour and consumer needs and expectations. Accordingly, there is an increasing awareness of the importance of including service quality indicators and quality specifications in contracts between operators and public transport authorities. The development of quality measures in the designing of contracts for public transport raises important aspects that must be considered. This paper examines issues concerning the definition of service quality measures for public transport. This will give a better understanding of pertinent questions and of improvement strategies open to public transport management. Next, it outlines some critical aspects that must be considered when including such measures in contracts between operators and public transport authorities.

Abstract
The computational requirements of a full physically-based global illumination solution are significant, currently precluding its solution on even a powerful modern PC in reasonable let alone real time. A key factor to consider if we are ever to achieve so-called "Realism in Real-Time", is that we are computing images for humans to look at. Although the human visual system is very good, it is by no means perfect. By understanding what the human does, or perhaps more importantly, does not see, enables us to save significant computation effort without any loss of perceptual quality of the resultant image. This paper describes the novel techniques of selective rendering which allow us to direct computational resources to those areas of high perceptual importance while avoiding computing any detail which will not be perceived by the viewer. Such selective rendering methods offer us the real possibility of achieving high fidelity graphics of complex scenes at interactive rates.

Abstract
This paper presents a methodology to implement PID (Proportional, Integral, Derivative) controllers in FPGAs (Field-Programmable Gate Arrays) using fixed-point numerical representation. The Matlab/Simulink environment is used for modeling, simulation and evaluation the performance provided by different fixed-point representations using a given control process. A static bit-width analyzer is used to give a specialized fixed-point representation for each operand/operator in the controller system. After bit-width analysis, a VHDL representation of the system is generated. Results show that the proposed methodology leads to shorten design cycles achieving important resource savings by employing specialized fixed-point representations.