2015
Authors
Silva, BA; Cuminato, LA; Bonato, V; Diniz, PC;
Publication
Proceedings, SBCCI 2015 - 28th Symposium on Integrated Circuits and Systems Design: Chip in Bahia
Abstract
Cache parameters such as size and associativity are fixed at manufacturing time which are often not tuned for the speciffc characteristics of each application code. The net re-sult is excessive energy consumption and lower performance. This paper explores the benefits of the use of a reconfig-urable data cache in terms of capacity and associativity in a LEON-3 embedded system. We present real energy and execution time results for a set of graph-based and numer-ical algorithms. For a combined application of these algo-rithms, the results reveal an aggregate energy savings of 7% and a execution time penalty of just 1% over the best fixed-Associativity cache architecture with the same capacity. We further explore the performance of a dynamic cache way shutdown adaptive algorithm and evaluate its performance and energy benefits in the context of the SLAM-EKF posi-tion estimation robotics algorithm. © 2015 ACM.
2015
Authors
Costa, J; Cardoso, JS;
Publication
ICPRAM (1)
Abstract
Ordinal data classification (ODC) has a wide range of applications in areas where human evaluation plays an important role, ranging from psychology and medicine to information retrieval. In ODC the output variable has a natural order; however, there is not a precise notion of the distance between classes. The Data Replication Method was proposed as tool for solving the ODC problem using a single binary classifier. Due to its characteristics, the Data Replication Method is straightforwardly mapped into methods that optimize the decision function globally. However, the mapping process is not applicable when the methods construct the decision function locally and iteratively, like decision trees and ADABOOST (with decision stumps). In this paper we adapt the Data Replication Method for ADABOOST, by softening the constraints resulting from the data replication process. Experimental comparison with state-of-the-art ADABOOST variants in synthetic and real data show the advantages of our proposal.
2015
Authors
Albano, Michele; Garibay-Martínez, Ricardo; Lino Ferreira, Luis;
Publication
INForum - Simpósio de Informática (INFORUM 2015).
Abstract
The Arrowhead project [1] considers to normalize all interactions involving embedded
systems by mediating them through services. The Service Oriented Architecture (SOA)
paradigm is applied to both the interactions that provide the service requested by the
user, and other support actions such as the authentication and registration of the devices,
and the services they provide, the look-up of devices and service provided, and orchestration
of services for creation of more complex services. To this purpose, services are
divided into Core Services, which are present in every environment supporting Arrowhead
applications, and user services that implement the applications. The Core Services
set comprises, at least, Authentication Service, Registration Service and Orchestration
Service.
2015
Authors
Pinho L.M.;
Publication
Ada User Journal
Abstract
2015
Authors
Maia, AC; Jacobina, CB; Freitas, NB; Vitorino, MA;
Publication
2015 IEEE Energy Conversion Congress and Exposition (ECCE)
Abstract
2015
Authors
Park, J; Diniz, PC;
Publication
ACM Transactions on Reconfigurable Technology and Systems
Abstract
There is an increasing concern about transient errors in deep submicron processor architectures. Softwareonly error detection approaches that exploit program invariants for silent error detection incur large execution overheads and are unreliable as state can be corrupted after invariant checkpoints. In this article, we explore the use of configurable hardware structures for the continuous evaluation of high-level program invariants at the assembly level. We evaluate the resource requirements and performance of the proposed predicate-evaluation hardware structures when integrated with a 32-bit MIPS soft core on a contemporary reconfigurable hardware device. The results, for a small set of kernel codes, reveal that these hardware structures require a very small number of hardware resources with negligible impact on the processor core that they are integrated in. Moreover, the amount of resources is fairly insensitive to the complexity of the invariants, thus making the proposed structures an attractive alternative to software-only predicate checking. Copyright © 2015 ACM.
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