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About

Vítor Grade Tavares earned his undergraduate and MSc degrees from the University of Aveiro, Portugal, and the Ph.D. degree from the Computational NeuroEngineering Laboratory, University of Florida, Gainesville, USA, in 2001, all in electrical engineering. He is currently an Assistant Professor at University of Porto and Senior Researcher at INESC-TEC, Porto. In 2010 he was a Visiting Professor at Carnegie Mellon University, USA. His research interests include low-power, mixed-signal and neuromorphic integrated-chip design and biomimetic computing, CMOS RF integrated circuit design for wireless sensor networks, and transparent electronics. He has coordinated several national projects, and also locally coordinated European projects. Most recent awards include co-recipient for the student best-paper award of the IEEE ICUWB 2014 and first place on TSMC design context in 90nm LP MS/RF in 2009. He was also awarded with a certificate of appreciation for contributions towards the advancement of IEEE and the Engineering Professions as Chair of the Education Society Chapter - Portugal section, which he co-founded.

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Publications

2021

A Neural Network Approach towards Generalized Resistive Switching Modelling

Authors
Carvalho, G; Pereira, M; Kiazadeh, A; Tavares, VG;

Publication
MICROMACHINES

Abstract
Resistive switching behaviour has been demonstrated to be a common characteristic to many materials. In this regard, research teams to date have produced a plethora of different devices exhibiting diverse behaviour, but when system design is considered, finding a 'one-model-fits-all' solution can be quite difficult, or even impossible. However, it is in the interest of the community to achieve more general modelling tools for design that allows a quick model update as devices evolve. Laying the grounds with such a principle, this paper presents an artificial neural network learning approach to resistive switching modelling. The efficacy of the method is demonstrated firstly with two simulated devices and secondly with a 4 mu m(2) amorphous IGZO device. For the amorphous IGZO device, a normalized root-mean-squared error (NRMSE) of 5.66 x 10(-3) is achieved with a [2, 50,50 ,1] network structure, representing a good balance between model complexity and accuracy. A brief study on the number of hidden layers and neurons and its effect on network performance is also conducted with the best NRMSE reported at 4.63 x 10(-3). The low error rate achieved in both simulated and real-world devices is a good indicator that the presented approach is flexible and can suit multiple device types.

2021

A Switching-Mode Power Recycling System for a Radio-Frequency Outphasing Transmitter

Authors
Saraiva, B; Duarte, C; Tavares, VG;

Publication
2021 XXXVI CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS21)

Abstract
This paper reports the development of a power recycling network for a wireless radio-frequency (RF) transmitter combiner. The transmitter makes use of two RF power amplifiers (PAs) in an outphasing architecture, connected at the output by a 180-degree hybrid combiner. In general, to provide isolation between the PAs and prevent nonlinear distortion, an isolation resistor is usually applied at the four-port combiner. However, the main drawback of such approach is the power dissipated at the isolation port, which drastically reduces the overall power efficiency of the outphasing transmitter. In the present work, the isolation port is replaced by an active network that provides the required input impedance for isolation, at the same time it converts the RF signal into dc, feeding it back to the transmitter power supply. Hence, this way, one recycles the power that would be lost in the isolating resistor. The proposed active network comprises a circulator, a resonant rectifier and a dc-dc converter that can be regulated by a maximum power point tracking (MPPT) algorithm. Simulation results for this power recycling system are provided, denoting 61-percent maximum efficiency achieved for an increase of 22-percent peak efficiency for QAM signals with a bandwidth of 250-kHz and carrier frequency equal to 250-MHz when operating at 41-miliwatt output power. © 2021 IEEE.

2021

Trade-offs and Limitations in Energy-Efficient Inverter-based CMOS Amplifiers

Authors
Correia, A; Tavares, VG; Barquinha, P; Goes, J;

Publication
2021 XXXVI CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS21)

Abstract
The operational transconductance amplifier (OTA) is, probably, the most relevant building block in analog circuits. However, its design has become particularly difficult in deep nanoscale CMOS technologies. Consequently, during the past decade, several inverter-based continuous-Time and switched-capacitor (SC) amplifier circuit solutions have been proposed to overcome the limitations imposed by deep-submicron processes. Inverters scale friendly with the technology downscaling, but their applicability depends on some key performance parameters such as, energy-efficiency, die area, low-frequency (DC) gain, gain-bandwidth product (GBW) and linearity versus output-swing (OS). This paper presents three inverter-based SC amplifiers, namely a single inverter, a three-stage inverter, and a three-stage inverter with a multipath. The key performance parameters are simulated and fairly compared. The impact of their linearity on systems, depending on the application, is also discussed. © 2021 IEEE.

2020

Rail-to-Rail Timing Signals Generation Using InGaZnO TFTs For Flexible X-Ray Detector

Authors
Bahubalindruni, PG; Tiwari, B; Pereira, M; Santa, A; Martins, J; Rovisco, A; Tavares, V; Martins, R; Fortunato, E; Barquinha, P;

Publication
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY

Abstract
This paper reports on-chip rail-to-rail timing signals generation thin-film circuits for the first time. These circuits, based on a-IGZO thin-film transistors (TFTs) with a simple staggered bottom gate structure, allow row and column selection of a sensor matrix embedded in a flexible radiation sensing system. They include on-chip clock generator (ring oscillator), column selector (shift register) and row-selector (a frequency divider and a shift register). They are realised with rail-to-rail logic gates with level-shifting ability that can perform inversion and NAND logic operations. These logic gates are capable of providing full output swing between supply rails, $V_{DD}$ and $V_{SS}$ , by introducing a single additional switch for each input in bootstrapping logic gates. These circuits were characterised under normal ambient atmosphere and show an improved performance compared to the conventional logic gates with diode connected load and pseudo CMOS counterparts. By using these high-performance logic gates, a complete rail-to-rail frequency divider is presented from measurements using D-Flip Flop. In order to realize a complete compact system, an on-chip ring oscillator (output clock frequency around 1 kHz) and a shift register are also presented from simulations, where these circuits show a power consumption of 1.5 mW and 0.82 mW at a supply voltage of 8 V, respectively. While the circuit concepts described here were designed for an X-ray sensing system, they can be readily expanded to other domains where flexible on-chip timing signal generation is required, such as, smart packaging, biomedical wearable devices and RFIDs.

2020

A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems

Authors
Miyandoab, FD; Ferreira, JC; Tavares, VMG; da Silva, JM; Velez, FJ;

Publication
IEEE-ACM TRANSACTIONS ON NETWORKING

Abstract

Supervised
thesis

2021

Towards a Digital-Twin Based, Multi-sided Market of Data-enabled Product-Services Systems

Author
Henrique Diogo Cardoso da Silva

Institution
UP-FEUP

2021

Memristor based logic circuits

Author
Luís Diogo de Almeida Outeiro

Institution
UP-FEUP

2021

Reciclagem de potência para um transmissor RF sem fios

Author
Bruno Miguel Gonçalves Saraiva

Institution
UP-FEUP

2021

Cellular Neural Networks design for sensor networks.

Author
João Luís Fernandes Ferreira

Institution
UP-FEUP

2021

Fake news

Author
Herbert Laroca Mendes Pinto

Institution