Cookies Policy
The website need some cookies and similar means to function. If you permit us, we will use those means to collect data on your visits for aggregated statistics to improve our service. Find out More
Accept Reject
  • Menu
About
Download Photo HD

About

Vítor Grade Tavares earned his undergraduate and MSc degrees from the University of Aveiro, Portugal, and the Ph.D. degree from the Computational NeuroEngineering Laboratory, University of Florida, Gainesville, USA, in 2001, all in electrical engineering. He is currently an Assistant Professor at University of Porto and Senior Researcher at INESC-TEC, Porto. In 2010 he was a Visiting Professor at Carnegie Mellon University, USA. His research interests include low-power, mixed-signal and neuromorphic integrated-chip design and biomimetic computing, CMOS RF integrated circuit design for wireless sensor networks, and transparent electronics. He has coordinated several national projects, and also locally coordinated European projects. Most recent awards include co-recipient for the student best-paper award of the IEEE ICUWB 2014 and first place on TSMC design context in 90nm LP MS/RF in 2009. He was also awarded with a certificate of appreciation for contributions towards the advancement of IEEE and the Engineering Professions as Chair of the Education Society Chapter - Portugal section, which he co-founded.

Interest
Topics
Details

Details

008
Publications

2020

Rail-to-Rail Timing Signals Generation Using InGaZnO TFTs For Flexible X-Ray Detector

Authors
Bahubalindruni, PG; Tiwari, B; Pereira, M; Santa, A; Martins, J; Rovisco, A; Tavares, V; Martins, R; Fortunato, E; Barquinha, P;

Publication
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY

Abstract
This paper reports on-chip rail-to-rail timing signals generation thin-film circuits for the first time. These circuits, based on a-IGZO thin-film transistors (TFTs) with a simple staggered bottom gate structure, allow row and column selection of a sensor matrix embedded in a flexible radiation sensing system. They include on-chip clock generator (ring oscillator), column selector (shift register) and row-selector (a frequency divider and a shift register). They are realised with rail-to-rail logic gates with level-shifting ability that can perform inversion and NAND logic operations. These logic gates are capable of providing full output swing between supply rails, $V_{DD}$ and $V_{SS}$ , by introducing a single additional switch for each input in bootstrapping logic gates. These circuits were characterised under normal ambient atmosphere and show an improved performance compared to the conventional logic gates with diode connected load and pseudo CMOS counterparts. By using these high-performance logic gates, a complete rail-to-rail frequency divider is presented from measurements using D-Flip Flop. In order to realize a complete compact system, an on-chip ring oscillator (output clock frequency around 1 kHz) and a shift register are also presented from simulations, where these circuits show a power consumption of 1.5 mW and 0.82 mW at a supply voltage of 8 V, respectively. While the circuit concepts described here were designed for an X-ray sensing system, they can be readily expanded to other domains where flexible on-chip timing signal generation is required, such as, smart packaging, biomedical wearable devices and RFIDs.

2020

A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems

Authors
Miyandoab, FD; Ferreira, JC; Tavares, VMG; da Silva, JM; Velez, FJ;

Publication
IEEE/ACM Transactions on Networking

Abstract

2019

IC Protection Against JTAG-based Attacks

Authors
Ren, XL; Torres, FP; Blanton, RD; Tavares, VG;

Publication
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Abstract
Security is now becoming a well-established challenge for integrated circuits (ICs). Various types of IC attacks have been reported, including reverse engineering IPs, dumping on-chip data, and controlling/modifying IC operation. IEEE 1149.1, commonly known as JTAG (Joint Test Action Group), is a standard for providing test access to an IC. JTAG is primarily used for IC manufacturing test, but also for in-field debugging and failure analysis since it gives access to internal sub-systems of the IC. Because the JTAG needs to be left intact and operational after fabrication, it inevitably provides a “backdoor” that can be exploited outside its intended use. This work proposes machine learning based approaches to detect illegitimate use of the JTAG. Specifically, JTAG operation is characterized using various features that are then classified as either legitimate or attack. Experiments using the OpenSPARC T2 platform demonstrate that the proposed approaches can classify legitimate JTAG operation and known attacks with significantly high accuracy. Experiments also demonstrate that unknown and disguised attacks can be detected with high accuracy as well (99% and 94%, respectively). IEEE

2019

Wearable sensor networks for human gait

Authors
Machado da Silva, J; Derogarian, F; Canas Ferreira, J; Grade Tavares, V;

Publication
Wearable Technologies and Wireless Body Sensor Networks for Healthcare

Abstract

2019

A precise low power and hardware-efficient time synchronization method for wearable systems

Authors
Derogarian, F; Canas Ferreira, J; Grade Tavares, V; Machado da Silva, J; Velez, FJ;

Publication
Wearable Technologies and Wireless Body Sensor Networks for Healthcare

Abstract

Supervised
thesis

2019

Design of a low power transmitter for UWB applications

Author
Iman Kianpour

Institution
UP-FEUP

2018

Double Channel PLL/DLL Based Clock Generation

Author
Pedro Alexandre Neves da Silva

Institution
UP-FEUP

2018

Design of a low power transmitter for UWB applications

Author
Iman Kianpour

Institution
UP-FEUP

2018

IC protection against JTAG/IJTAG-based attacks

Author
Xuanle Ren

Institution
UP-FEUP

2018

Low-pass CMOS Sigma-Delta Converter

Author
Diogo Dinis da Fonseca

Institution
UP-FEUP