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About

About

Vítor Grade Tavares earned his undergraduate and MSc degrees from the University of Aveiro, Portugal, and the Ph.D. degree from the Computational NeuroEngineering Laboratory, University of Florida, Gainesville, USA, in 2001, all in electrical engineering. He is currently an Assistant Professor at University of Porto and Senior Researcher at INESC-TEC, Porto. In 2010 he was a Visiting Professor at Carnegie Mellon University, USA. His research interests include low-power, mixed-signal and neuromorphic integrated-chip design and biomimetic computing, CMOS RF integrated circuit design for wireless sensor networks, and transparent electronics. He has coordinated several national projects, and also locally coordinated European projects. Most recent awards include co-recipient for the student best-paper award of the IEEE ICUWB 2014 and first place on TSMC design context in 90nm LP MS/RF in 2009. He was also awarded with a certificate of appreciation for contributions towards the advancement of IEEE and the Engineering Professions as Chair of the Education Society Chapter - Portugal section, which he co-founded.

Interest
Topics
Details

Details

005
Publications

2018

Detection of IJTAG attacks using LDPC-based feature reduction and machine learning

Authors
Ren, XL; Blanton, RDS; Tavares, VG;

Publication
Proceedings of the European Test Workshop

Abstract
IEEE 1687 standard (IJTAG), as an extension to the IEEE 1149.1, facilitates efficient access to embedded instruments by supporting reconfigurable scan networks. Specifically, IJTAG allows each IP to be wrapped by a test data register (TDR) whose access is controlled by a segment insertion bit (SIB) or a scan-mux control bit (SCB). Because the TDRs and the SIB/SCB network are typically not public, but critical for accessing embedded instruments, they might be used for illegitimate purposes, such as dumping credential data and reverse engineering IP design. Machine learning has been proposed to detect such attacks, but the large number of instruments and parallel execution enabled by the IJTAG produce high-dimensional data, which poses a challenge to on-chip detection. In this paper, we propose to reduce the high-dimensional but sparse data using a low-density parity-check (LDPC) matrix. Experiments using a modified version of the OpenSPARC T2 to include IJTAG functionality demonstrate that the use of feature reduction eliminates 91% of the features, leading to 43% reduction in circuit size without affecting detection accuracy. Also, the on-chip detector adds moderate overhead (~ 8%) to the IJTAG. © 2018 IEEE.

2018

High-Gain Transimpedance Amplifier for Flexible Radiation Dosimetry Using InGaZnO TFTs

Authors
Bahubalindruni, PG; Martins, J; Santa, A; Tavares, V; Martins, R; Fortunato, E; Barquinha, P;

Publication
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY

Abstract
This paper presents a novel high-gain transimpedance amplifier for flexible radiation sensing systems that can be used as large-area dosimeters. The circuit is implemented with indium-gallium-zinc-oxide thin-film-transistors and uses two stages for the amplification of the sensor signal (current). The first stage consists of cascode current mirrors with a diode connected load that performs current amplification and voltage conversion. Then, the first stage is followed by a voltage amplifier based on a positive feedback topology for gain enhancement. The proposed circuit converts nano-ampere (10 nA) currents into hundreds of millivolts (280 mV), showing a gain around 149 dB and a power consumption of 0.45 mW. The sensed radiation dose level, in voltage terms, can drive the next stages in the radiation sensing system, such as analog to digital converters. These radiation sensing devices can find potential applications in real-time, large area, flexible health, and security systems.

2017

A Low-Power Analog Adder and Driver Using a-IGZO TFTs

Authors
Bahubalindruni, PG; Tavares, VG; Martins, R; Fortunato, E; Barquinha, P;

Publication
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

Abstract
This paper presents a novel low-power analog circuit, with n-type IGZO TFTs that can function as an adder operator or be designed to operate as a driver. Experiments were set to show summation of up to four signals. However, the design can easily be expanded to add higher number of signals, by appending a single TFT at the input per each additional signal. The circuit is simple, uses a single power supply irrespective to the number of input voltage signals, and shows good accuracy over a reasonable range of input values. By choosing proper TFT dimensions, the topology can replace the typical output drivers of TFT amplifiers, namely the common-drain with current source biasing, or the common-source with diode connected load. The circuit was fabricated with a temperature that does not exceeds 200 degrees C. Its performance is characterized from measurements at room temperature and normal ambient, with a power supply voltage of 12 V and a load of approximate to 4 pF. The proposed circuit has shown a linearity error less than 3.2% (up to an input signal peak-to-peak value of 2 V), a power consumption of 78 mu W and a bandwidth of approximate to 115 kHz, under worst case condition (when it is adding four signals with the same frequency). It has shown superior performance in terms of linearity when compared to the typical drivers considered in this study. In addition, it has shown almost the same behavior when measurements were repeated after one year. Therefore, the proposed circuit is a robust viable alternative to conventional approaches, being more compact, and contributes to increase the functionality of large-area flexible electronics.

2017

Europe and the Future for WPT COST Action IC1301 Team

Authors
Carvalho, NB; Georgiadis, A; Costanzo, A; Stevens, N; Kracek, J; Pessoa, L; Roselli, L; Dualibe, F; Schreurs, D; Mutlu, S; Rogier, H; Visser, H; Takacs, A; Rocca, P; Dimitriou, A; Michalski, J; Raida, Z; Tedjini, S; Joseph, W; Duroc, Y; Sahalos, JN; Bletsas, A; Samaras, T; Nikoletseas, S; Raptis, TP; Boaventura, A; Collado, A; Trevisan, R; Minnaert, B; Svanda, M; Pereira, M; Mongiardo, M; Popov, G; Pan, N; Aubert, H; Viani, F; Siachalou, S; Kant, P; Vera, GA; Polycarpou, AC; Cruz, P; Mastri, F; Mazanek, M; Santos, H; Alimenti, F; Garcia Vazquez, H; Pollin, S; Poli, L; Belo, D; Masotti, D; Machac, J; Tavares, V; Mezzanotte, P; Ndungidi, P; Oliveri, G; Fernandes, R; Salgado, H; Moeyaert, V; Massa, A; Goncalves, R; Pinho, P; Monti, G; Tarricone, L; Dionigi, M; Russer, P; Russer, J;

Publication
IEEE MICROWAVE MAGAZINE

Abstract

2017

A complementary LC-tank based IR-UWB pulse generator for BPSK modulation

Authors
Kianpour, I; Hussain, B; Tavares, VG;

Publication
2017 IEEE East-West Design & Test Symposium (EWDTS)

Abstract

Supervised
thesis

2017

CMOS RF Sigma-Delta Converter

Author
Luís Filipe Brochado Reis

Institution
UP-FEUP

2017

Operation and reconstruction of signals based on integrate-and-fire conversion using FPGA

Author
Guilherme Luis Leitão Teixeira Guia de Carvalho

Institution
UP-FEUP

2016

Integrated Systems Security through User Behavior and System Activity Analyzes via Machine Learning

Author
Xuanle Ren

Institution
UP-FEUP

2016

Inductorless DC\DC converter

Author
Fábio Miguel Ferreira Pascoal

Institution
UP-FEUP

2015

Learning system for IC security

Author
Francisco Carvalho Viana Pimentel Torres

Institution
UP-FEUP