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Sobre

Vítor Grade Tavares obteve a sua licenciatura e mestrado pela Universidade de Aveiro, Portugal, e o doutoramento no Computational NeuroEngineering Laboratory, University of Florida, Gainesville, USA, em 2001, ambos em engenharia eletrotécnica. É atualmente Professor Auxiliar na Universidade do Porto e Investigador Sénior do INESC-TEC, Porto. Em 2010 foi Professor Visitante na Carnegie Mellon University, EUA. Os seus interesses de investigação incluem desenho de circuitos integrados de baixa potência, de sinal misto e computação neuro-mórfica e bio-mimética, projeto de circuitos integrados CMOS RF para redes de sensores sem fio e eletrónica transparente. Tem coordenado vários projetos nacionais, bem como tem coordenado localmente projetos europeus. Os prêmios mais recentes incluem codestinatário do prêmio de melhor artigo no IEEE ICUWB 2014 e primeiro lugar no concurso de desenho TSMC em 90nm LP MS / RF em 2009. Também foi premiado com um certificado de agradecimento por contribuições para o avanço do IEEE e das Profissões de Engenharia como Presidente da secção da Sociedade de Educação - Portugal, que cofundou.

Tópicos
de interesse
Detalhes

Detalhes

008
Publicações

2020

Rail-to-Rail Timing Signals Generation Using InGaZnO TFTs For Flexible X-Ray Detector

Autores
Bahubalindruni, PG; Tiwari, B; Pereira, M; Santa, A; Martins, J; Rovisco, A; Tavares, V; Martins, R; Fortunato, E; Barquinha, P;

Publicação
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY

Abstract
This paper reports on-chip rail-to-rail timing signals generation thin-film circuits for the first time. These circuits, based on a-IGZO thin-film transistors (TFTs) with a simple staggered bottom gate structure, allow row and column selection of a sensor matrix embedded in a flexible radiation sensing system. They include on-chip clock generator (ring oscillator), column selector (shift register) and row-selector (a frequency divider and a shift register). They are realised with rail-to-rail logic gates with level-shifting ability that can perform inversion and NAND logic operations. These logic gates are capable of providing full output swing between supply rails, $V_{DD}$ and $V_{SS}$ , by introducing a single additional switch for each input in bootstrapping logic gates. These circuits were characterised under normal ambient atmosphere and show an improved performance compared to the conventional logic gates with diode connected load and pseudo CMOS counterparts. By using these high-performance logic gates, a complete rail-to-rail frequency divider is presented from measurements using D-Flip Flop. In order to realize a complete compact system, an on-chip ring oscillator (output clock frequency around 1 kHz) and a shift register are also presented from simulations, where these circuits show a power consumption of 1.5 mW and 0.82 mW at a supply voltage of 8 V, respectively. While the circuit concepts described here were designed for an X-ray sensing system, they can be readily expanded to other domains where flexible on-chip timing signal generation is required, such as, smart packaging, biomedical wearable devices and RFIDs.

2019

IC Protection Against JTAG-based Attacks

Autores
Ren, XL; Torres, FP; Blanton, RD; Tavares, VG;

Publicação
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Abstract
Security is now becoming a well-established challenge for integrated circuits (ICs). Various types of IC attacks have been reported, including reverse engineering IPs, dumping on-chip data, and controlling/modifying IC operation. IEEE 1149.1, commonly known as JTAG (Joint Test Action Group), is a standard for providing test access to an IC. JTAG is primarily used for IC manufacturing test, but also for in-field debugging and failure analysis since it gives access to internal sub-systems of the IC. Because the JTAG needs to be left intact and operational after fabrication, it inevitably provides a “backdoor” that can be exploited outside its intended use. This work proposes machine learning based approaches to detect illegitimate use of the JTAG. Specifically, JTAG operation is characterized using various features that are then classified as either legitimate or attack. Experiments using the OpenSPARC T2 platform demonstrate that the proposed approaches can classify legitimate JTAG operation and known attacks with significantly high accuracy. Experiments also demonstrate that unknown and disguised attacks can be detected with high accuracy as well (99% and 94%, respectively). IEEE

2019

Wearable sensor networks for human gait

Autores
Machado da Silva, J; Derogarian, F; Canas Ferreira, J; Grade Tavares, V;

Publicação
Wearable Technologies and Wireless Body Sensor Networks for Healthcare

Abstract

2019

A precise low power and hardware-efficient time synchronization method for wearable systems

Autores
Derogarian, F; Canas Ferreira, J; Grade Tavares, V; Machado da Silva, J; Velez, FJ;

Publicação
Wearable Technologies and Wireless Body Sensor Networks for Healthcare

Abstract

2019

A reliable wearable system for BAN applications with a high number of sensors and high data rate

Autores
Derogarian, F; Canas Ferreira, J; Grade Tavares, V; Machado da Silva, J; Velez, FJ;

Publicação
Wearable Technologies and Wireless Body Sensor Networks for Healthcare

Abstract

Teses
supervisionadas

2019

Design of a low power transmitter for UWB applications

Autor
Iman Kianpour

Instituição
UP-FEUP

2018

Double Channel PLL/DLL Based Clock Generation

Autor
Pedro Alexandre Neves da Silva

Instituição
UP-FEUP

2018

Low-pass CMOS Sigma-Delta Converter

Autor
Diogo Dinis da Fonseca

Instituição
UP-FEUP

2018

Design of a low power transmitter for UWB applications

Autor
Iman Kianpour

Instituição
UP-FEUP

2018

IC protection against JTAG/IJTAG-based attacks

Autor
Xuanle Ren

Instituição
UP-FEUP