Informática, Eletrónica e Sistemas Digitais, Electrónica Digital, Microprocessadores, Sistemas Heterogéneos
Work description
The combination of RISC-V processors with dedicated accelerators is especially promising for edge computing; among these, CGRAs (Coarse Grained Reconfigurable Arrays) stand out for their efficiency and flexibility. However, their use is still limited by integration difficulties and poorly standardized programming models. This grant explores the use of custom RISC-V instructions as a standardizable integration mechanism, allowing abstraction in the compilation process and transparency in the use of the CGRA by software. Specific objectives: - Adapt an existing state-of-the-art CGRA for integration with a RISC-V processor through custom instructions; - Validate the functional integration between RISC-V core and CGRA using in-house co-simulation methods, and simulations of CGRA designs available in the state-of-the-art; - Writing a co-authored scientific article to disseminate the results obtained.
Academic Qualifications
Bachelor's degree or enrollment in a master's degree in electrical engineering, computer science, or a related field;
Minimum profile required
Experience in HDL and C++Fluency in English (written and spoken)
Preference factors
Experience in RISC-V Experience in FPGA or heterogeneous systems Fluent in Portuguese and English (written and spoken)
Application Period
Since 08 Aug 2025 to 22 Aug 2025
Centre
Telecommunications and Multimedia