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About

I received my Master's Degree from FEUP (Faculdade de Engenharia da Universidade do Porto), in Electrical and Computer Engineering. My thesis was titled Generation of Reconfigurable Circuits from Machine Code, a work which continued throughout my PhD in Electrical and Computer Engineering, also at FEUP, and in association with INESC-TEC.

Having completed my PhD thesis, Generation of Custom Run-time Reconfigurable Hardware for Transparent Binary Acceleration, I am now a post-doc researcher with INESC-TEC on the topic of special compilers for hardware, and also an Auxiliary Assistant Professor with the Department of Informatics at FEUP.

Interest
Topics
Details

Details

003
Publications

2021

A Binary Translation Framework for Automated Hardware Generation

Authors
Paulino, N; Bispo, J; Ferreira, JC; Cardoso, JMP;

Publication
IEEE Micro

Abstract

2020

Improving performance and energy consumption in embedded systems via binary acceleration: A survey

Authors
Paulin, N; Ferreira, JC; Cardoso, JMP;

Publication
ACM Computing Surveys

Abstract
The breakdown of Dennard scaling has resulted in a decade-long stall of the maximum operating clock frequencies of processors. To mitigate this issue, computing shifted to multi-core devices. This introduced the need for programming flows and tools that facilitate the expression of workload parallelism at high abstraction levels. However, not all workloads are easily parallelizable, and the minor improvements to processor cores have not significantly increased single-threaded performance. Simultaneously, Instruction Level Parallelism in applications is considerably underexplored. This article reviews notable approaches that focus on exploiting this potential parallelism via automatic generation of specialized hardware from binary code. Although research on this topic spans over more than 20 years, automatic acceleration of software via translation to hardware has gained new importance with the recent trend toward reconfigurable heterogeneous platforms. We characterize this kind of binary acceleration approach and the accelerator architectures on which it relies. We summarize notable state-of-the-art approaches individually and present a taxonomy and comparison. Performance gains from 2.6× to 5.6× are reported, mostly considering bare-metal embedded applications, along with power consumption reductions between 1.3× and 3.9×. We believe the methodologies and results achievable by automatic hardware generation approaches are promising in the context of emergent reconfigurable devices. © 2020 Association for Computing Machinery.

2020

Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets

Authors
Paulino, N; Ferreira, JC; Cardoso, JMP;

Publication
IEEE Access

Abstract

2020

Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework

Authors
Paulino, N; Ferreira, JC; Bispo, J; Cardoso, JMP;

Publication
30th International Conference on Field-Programmable Logic and Applications, FPL 2020, Gothenburg, Sweden, August 31 - September 4, 2020

Abstract

2019

Dynamic Partial Reconfiguration of Customized Single-Row Accelerators

Authors
Paulino, NMC; Ferreira, JC; Cardoso, JMP;

Publication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Abstract

Supervised
thesis

2020

Dynamically Reconfigurable Multi-Classifier Architecture on FPGA

Author
Joana Lima Macedo

Institution
UP-FEUP

2020

An Exploration of FPGAs as Accelerators for Graph Analysis via High-Level Synthesis

Author
Pedro Filipe Vilhena de Campos Oliveira e Silva

Institution
UP-FEUP

2020

Run-Time Selection of Customized Accelerators

Author
José Miguel Carvalho Martins de Campos

Institution
UP-FEUP

2020

Vehicle Tracking in Warehouses via Bluetooth Beacon Angle-of-Arrival

Author
Telmo Francisco da Costa Soares

Institution
UP-FEUP

2020

Generating Hardware Modules via Binary Translation of RISC-V Binaries

Author
João Miguel Curado Conceição

Institution
UP-FEUP