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About

I received my Master's Degree from FEUP (Faculdade de Engenharia da Universidade do Porto), in Electrical and Computer Engineering. My thesis was titled Generation of Reconfigurable Circuits from Machine Code, a work which continued throughout my PhD in Electrical and Computer Engineering, also at FEUP, and in association with INESC-TEC.

Having completed my PhD thesis, Generation of Custom Run-time Reconfigurable Hardware for Transparent Binary Acceleration, I am now a post-doc researcher with INESC-TEC on the topic of special compilers for hardware, and also an Auxiliary Assistant Professor with the Department of Informatics at FEUP.

Interest
Topics
Details

Details

003
Publications

2021

A Binary Translation Framework for Automated Hardware Generation

Authors
Paulino, N; Bispo, J; Ferreira, JC; Cardoso, JMP;

Publication
IEEE Micro

Abstract

2021

On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators

Authors
Santos, T; Paulino, N; Bispo, J; Cardoso, JMP; Ferreira, JC;

Publication
International Conference on Field-Programmable Technology, (IC)FPT 2021, Auckland, New Zealand, December 6-10, 2021

Abstract

2021

Evaluating a Novel Bluetooth 5.1 AoA Approach for Low-Cost Indoor Vehicle Tracking via Simulation

Authors
Paulino, N; Pessoa, LM; Branquinho, A; Goncalves, E;

Publication
2021 JOINT EUROPEAN CONFERENCE ON NETWORKS AND COMMUNICATIONS & 6G SUMMIT (EUCNC/6G SUMMIT)

Abstract
The recent Bluetooth 5.1 specification introduced the use of Angle-of-Arrival (AoA) information which enables the design of novel low-cost indoor positioning systems. Existing approaches rely on multiple fixed gateways equipped with antenna arrays, in order to determine the location of an arbitrary number of simple mobile omni-directional emitters. In this paper, we instead present an approach where mobile receivers are equipped with antenna arrays, and the fixed infrastructure is composed of battery-powered beacons. We implement a simulator to evaluate the solution using a real-world data set of AoA measurements. We evaluated the solution as a function of the number of beacons, their transmission period, and algorithmic parameters of the position estimation. Sub-meter accuracy is achievable using 1 beacon per 15 m(2) and a beacon transmission period of 500 ms.

2021

FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example

Authors
Silva, PF; Bispo, J; Paulino, N;

Publication
International Conference on Field-Programmable Technology, (IC)FPT 2021, Auckland, New Zealand, December 6-10, 2021

Abstract

2020

Improving performance and energy consumption in embedded systems via binary acceleration: A survey

Authors
Paulin, N; Ferreira, JC; Cardoso, JMP;

Publication
ACM Computing Surveys

Abstract
The breakdown of Dennard scaling has resulted in a decade-long stall of the maximum operating clock frequencies of processors. To mitigate this issue, computing shifted to multi-core devices. This introduced the need for programming flows and tools that facilitate the expression of workload parallelism at high abstraction levels. However, not all workloads are easily parallelizable, and the minor improvements to processor cores have not significantly increased single-threaded performance. Simultaneously, Instruction Level Parallelism in applications is considerably underexplored. This article reviews notable approaches that focus on exploiting this potential parallelism via automatic generation of specialized hardware from binary code. Although research on this topic spans over more than 20 years, automatic acceleration of software via translation to hardware has gained new importance with the recent trend toward reconfigurable heterogeneous platforms. We characterize this kind of binary acceleration approach and the accelerator architectures on which it relies. We summarize notable state-of-the-art approaches individually and present a taxonomy and comparison. Performance gains from 2.6× to 5.6× are reported, mostly considering bare-metal embedded applications, along with power consumption reductions between 1.3× and 3.9×. We believe the methodologies and results achievable by automatic hardware generation approaches are promising in the context of emergent reconfigurable devices. © 2020 Association for Computing Machinery.

Supervised
thesis

2021

Generating Hardware Modules via Binary Translation of RISC-V Binaries

Author
João Miguel Curado Conceição

Institution
UP-FEUP

2021

Vehicle Tracking in Warehouses via Bluetooth Beacon Angle-of-Arrival

Author
Telmo Francisco da Costa Soares

Institution
UP-FEUP

2021

An Exploration of FPGAs as Accelerators for Graph Analysis via High-Level Synthesis

Author
Pedro Filipe Vilhena de Campos Oliveira e Silva

Institution
UP-FEUP

2021

Indoor Bluetooth Low Energy Direction Finding via Circular Antenna Array

Author
Catarina Alexandra Rodrigues Marques

Institution
IPP-ISEP

2021

Runtime Management of Heterogeneous Compute Resources in Embedded Systems

Author
Luís Miguel Mendes Pimentel Alves de Sousa

Institution
UP-FEUP