Eletrical Engineering
Work description
Study of the state of the art in CPU–CGRA interface mechanisms, including approaches using custom ISA extensions; Definition of the set of customized instructions for CGRA control (e.g., configuration, execution, reading results); Implementation of the hardware interface between the RISC-V core and CGRA, either in hardware (via HLS or HDL) or via a co-simulation system; Contribute to or use a binary generation method for the system, converting mapped graphs to instruction sequences, and execute test programs; Collaborate in writing scientific articles to disseminate results.
Academic Qualifications
Master's degree in electrical engineering, computer science, or related field.
Minimum profile required
experience in hardware design or heterogeneous systemsprogramming experience in C/C++ languagefuent in English (written and spoken)
Preference factors
Experience with RISC-V Experience manipulating graph-structured data Fluent in Portuguese and English (written and spoken)
Application Period
Since 04 Dec 2025 to 19 Dec 2025
Centre
Telecommunications and Multimedia