Abstract

Abstract
The vast datasets produced in human genomics must be efficiently stored, transferred, and processed while prioritizing storage space and restore performance. Balancing these two properties becomes challenging when resorting to traditional data compression techniques. In fact, specialized algorithms for compressing sequencing data favor the former, while large genome repositories widely resort to generic compressors (e.g., GZIP) to benefit from the latter. Notably, human beings have approximately 99.9 percent of DNA sequence similarity, vouching for an excellent opportunity for deduplication and its assets: leveraging inter-file similarity and achieving higher read performance. However, identity-based deduplication fails to provide a satisfactory reduction in the storage requirements of genomes. In this article, we balance space savings and restore performance by proposing GenoDedup, the first method that integrates efficient similarity-based deduplication and specialized delta-encoding for genome sequencing data. Our solution currently achieves 67.8 percent of the reduction gains of SPRING (i.e., the best specialized tool in this metric) and restores data 1.62x faster than SeqDB (i.e., the fastest competitor). Additionally, GenoDedup restores data 9.96x faster than SPRING and compresses files 2.05x more than SeqDB.

Abstract
We discuss the concept of FPGA-unfriendliness, the property of certain algorithms, programs, or domains which may limit their applicability to FPGAs. Specifically, we look at graph analysis, which has recently seen increased interest in combination with High-Level Synthesis, but has yet to find great success compared to established acceleration mechanisms. To this end, we make use of Xilinx's Vitis Graph Library to implement Single-Source Shortest Paths (SSSP) and PageRank (PR), and present a custom kernel written from the ground up for Distinctiveness Centrality (DC, a novel graph centrality measure). We use public datasets to test these implementations, and analyse power consumption and execution time. Our comparisons against published data for GPU and CPU execution show FPGA slowdowns in execution time between around 18.5x and 328x for SSSP, and around 1.8x and 195x for PR, respectively. In some instances, we obtained FPGA speedups versus CPU of up to 2.5x for PR. Regarding DC, results show speedups from 0.1x to 3.5x, and energy efficiency increases from 0.8x to 6x. Lastly, we provide some insights regarding the applicability of FPGAs in FPGA-unfriendly domains, and comment on the future as FPGA and HLS technology advances.

Abstract
Computer-aided design (CAD) and 3D modeling are similar, but they have different functionalities and applications. CAD is a fundamental tool to create object models, design parts, and create 2D schematics from 3D designed objects that can later be used in manufacturing. Meanwhile, 3D modeling is mostly used in entertainment, to create meshes for animation and games. When there is the necessity of using real-life object models in game engines, a conversion process is required to go from CAD to 3D meshes. Converting from the continuous domain of CAD to the discrete domain of 3D models represents a trade-off between processing cost and visual accuracy, in order to obtain the best user experience. This work explores different methods for the creation of meshes and the reduction of the number of polygons used to represent them. Based on these concepts, an interactive application was created to allow the users to control how the model looks in the game engine, in a simple way, while also optimizing and simplifying the mapping of textures for the generated meshes. This application (CADto3D) generates accurate 3D models based on CAD surfaces while giving the user more control over the final result than other current solutions.

Abstract
The paper presents the e-facilitator concept and explores the perspective of some professionals in the field (stakeholders) on this role and its competencies. Facilitation in virtual learning environments is a growing challenge when more and more learners find their way to online learning platforms and many universities adapt their courses to digital environments since the global pandemic forced many people to stay at home.

Abstract
As applications move to the edge, efficiency in computing power and power/energy consumption is required. Heterogeneous computing promises to meet these requirements through application-specific hardware accelerators. Runtime adaptivity might be of paramount importance to realize the potential of hardware specialization, but further study is required on workload retargeting and offloading to reconfigurable hardware. This article presents our framework for the exploration of both offloading and hardware generation techniques. The framework is currently able to process instruction sequences from MicroBlaze, ARMv8, and riscv32imaf binaries, and to represent them as Control and Dataflow Graphs for transformation to implementations of hardware modules. We illustrate the framework's capabilities for identifying binary sequences for hardware translation with a set of 13 benchmarks.