Abstract

Abstract

Abstract

Abstract
Higher-order statistics extend the analysis methods of non-linear systems and non-gaussian signals based on the autocorrelation and power spectrum. The main drawback of their use in real time applications is the high complexity of their estimation due to the large number of arithmetic operations. This paper presents an experimental vector architecture for the estimation of the higher-order moments. The processor's core is a pipelined multiply-accumulate unit that receives four data vectors and computes in parallel the moment taps up to the fourth-order. The design of custom cache memory organization and address generation circuits has led to more than 11 operations per clock cycle. The architecture was modeled and simulated in Verilog and is presently being implemented in XILINX field-programmable gate arrays (FPGAs) and one custom integrated circuit for the multiply-accumulate unit.

Abstract
This paper presents experiments carried out with a prototype test chip provided by the IEEE P1149.4 Mixed-Signal Testing Working Group, which explore the architecture of the proposed analogue boundary module to implement simultaneous observation of power supply current and output voltage, towards mixed current/voltage testing of analogue and mixed-signal circuits.

Abstract
Higher-order statistics (HOS) are a powerful analysis tool in digital signal processing. The most difficult task to use it effectively is the estimation of higher-order moments of sampled data, taken from real systems. For applications that require real-time processing, the performance achieved by common microprocessors or digital signal processors is not good enough to carry out the large number of calculations needed for their estimation. This paper presents ProHos-1, an experimental vector processor for the estimation of the higher-order moments up to the fourth-order. The processor's architecture exploits the structure of the algorithm, to process in parallel four vectors of the input data in a pipe-lined fashion, executing the equivalent to 11 operations in each clock cycle. The design of dedicated control circuits led to high clock rate and small hardware complexity, thus suitable for implementation as an ASIC (Application Specific integrated Circuit).