2012
Authors
Ribeiro, J; Moura, R; Flores, D; Lopes, DB; Gouveia, C; Mendonca, S; Frazao, O;
Publication
Coal and Peat Fires: A Global Perspective
Abstract
2012
Authors
Martins, M; Correia, V; Cabral, JM; Lanceros Mendez, S; Rocha, JG;
Publication
SENSORS AND ACTUATORS A-PHYSICAL
Abstract
Ultrasound transducers are typically based on piezoelectric materials, due to their good response at high frequencies. Depending on the application, ceramics, polymers and composite materials can be used. In this work, an optimization study of ultrasound transducers for underwater communications is addressed, focusing on a piston type emitter transducer operating in thickness mode (d(33)). The piston is constituted by an active element disk with optimized dimensions. It is discussed how the acoustic impedance, thickness, resonance frequency and structure affect the transducer performance. This work allows a better understanding of the emitter transducer characteristics allowing reaching the optimum point of operation for specific applications. Focusing on underwater communication, the acoustic channel is defined and the transducer is optimized by finite element computer simulations. The results were compared with experimental tests, which show that four-layer structures increase up to 16 dB in performance versus single-layer.
2011
Authors
Restivo, MT; Alves, JC; Cardoso, A;
Publication
iJEP
Abstract
2011
Authors
Cardoso, JMP; Diniz, PC; Petrov, Z; Bertels, K; Hübner, M; van Someren, H; Gonçalves, F; de Coutinho, JGF; Constantinides, GA; Olivier, B; Luk, W; Becker, J; Kuzmanov, G; Thoma, F; Braun, L; Kühnle, M; Nane, R; Sima, VM; Krátký, K; Alves, JC; Ferreira, JC;
Publication
Reconfigurable Computing
Abstract
2011
Authors
Restivo, MT; Alves, JC; Cardoso, A;
Publication
International Journal of Engineering Pedagogy (iJEP) - Int. J. Eng. Ped.
Abstract
2011
Authors
Alves, JC; Diniz, PC;
Publication
Proceedings of the 2011 7th Southern Conference on Programmable Logic, SPL 2011
Abstract
This paper describes a micro-architecture for a custom programmable FPGA-based processor, with direct support for streaming and vector computations relying on custom cache memory storage. The processor combines a custom data-path with several parallel data ports for accessing operands in streaming mode thus efficiently supporting nested looping constructs found in high-level languages while mitigating the impact on external memory bandwidth. The architecture leverages the strided access patterns of streaming data access using a microcoded sequencer with multi-dimensional nested looping capability. We present synthesis results for the main components of the architecture on a Xilinx's Virtex-4 FPGA device. The results reveal the architecture to be extremely flexible and consume few FPGA resources. © 2011 IEEE.
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