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Publications

Publications by João Paiva Cardoso

2019

Supporting the Scale-up of High Performance Application to Pre-Exascale Systems: The ANTAREX Approach

Authors
Silvano, C; Agosta, G; Bartolini, A; Beccari, AR; Benini, L; Besnard, L; Bispo, J; Cmar, R; Cardoso, JMP; Cavazzoni, C; Cesarini, D; Cherubin, S; Ficarelli, F; Gadioli, D; Golasowski, M; Lasri, I; Libri, A; Manelfi, C; Martinovic, J; Palermo, G; Pinto, P; Rohou, E; Sanna, N; Slaninová, K; Vitali, E;

Publication
2019 27TH EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED AND NETWORK-BASED PROCESSING (PDP)

Abstract
The ANTAREX project developed an approach to the performance tuning of High Performance applications based on an Aspect-oriented Domain Specific Language (DSL), with the goal to simplify the enforcement of extra-functional properties in large scale applications. The project aims at demonstrating its tools and techniques on two relevant use cases, one in the domain of computational drug discovery, the other in the domain of online vehicle navigation. In this paper, we present an overview of the project and of its main achievements, as well as of the large scale experiments that have been planned to validate the approach.

2018

Formal verification of a domain specific language for run-time adaptation

Authors
Khan, S; Khalid, F; Hasan, O; Cardoso, JMP;

Publication
SysCon

Abstract
Compared to general purpose programming languages, domain specific languages (DSLs) targeting adaptive embedded software development provide a very promising alternative for developing clean and error free run-time adaptations. However, the ability to use several rules in a single adaptation strategy, as allowed by some DSLs, may lead to conflicts and reachability issues, which can eventually lead to functional bugs. Traditionally, such conflict analysis is done using software testing or manual manipulation of automata based models of rules. However, both of these techniques are error-prone and thus can lead to unwanted situations. As an accurate alternative, we propose to use model checking for rule conflict and reachability analysis in DSL adaptation. In particular, this paper provides an approach to formally model DSL adaptation specifications, along with their rules, and identifies a set of generic temporal properties to check for reachability and other rule conflicts, using the finite and infinite state-space based model checking capabilities of nuXmv model checker. For illustration, formal analyses of an energy aware CPU scheduling algorithm, i.e, PAST, for adaptivity rules for a stereo navigation system and for a context aware application are presented.

2019

Graph-Based Code Restructuring Targeting HLS for FPGAs

Authors
Ferreira, AC; Cardoso, JMP;

Publication
ARC

Abstract
High-level synthesis (HLS) is of paramount importance to enable software developers to map critical computations to FPGA-based hardware accelerators. However, in order to generate efficient hardware accelerators one needs to apply significant code transformations and adequately use the directive-driven approach, part of most HLS tools. The code restructuring and directives needed are dependent not only of the characteristics of the input code but also of the HLS tools and target FPGAs. These aspects require a deep knowledge about the subjects involved and tend to exclude software developers. This paper presents our recent approach for automatic code restructuring targeting HLS tools. Our approach uses an unfolded graph representation, which can be generated from program execution traces, and graph-based optimizations, such as folding, to generate suitable HLS C code. In this paper, we describe the approach and the new optimizations proposed. We evaluate the approach with a number of representative kernels and the results show its capability to generating efficient hardware implementations only achievable using manual restructuring of the input software code and manual insertion of adequate HLS directives.

2019

Nonio - modular automatic compiler phase selection and ordering specialization framework for modern compilers

Authors
Nobre, R; Bispo, J; Carvalho, T; Cardoso, JMP;

Publication
SOFTWAREX

Abstract
This article presents Nonio, a modular, easy-to-use, design space exploration framework focused on exploring custom combinations of compiler flags and compiler sequences. We describe the framework and discuss its use with two of the most popular compiler toolchains, GCC and Clang+LLVM. Particularly, we discuss implementation details in the context of flag selection, when using GCC, and phase selection and ordering, when using Clang+LLVM. The framework software organization allows to easily add new components as plug-ins (e.g., an exploration algorithm, an objective metric, integration with another compiler toolchain). The software architecture provides well-defined interfaces, in order to enable seamless composition and interaction between different components. We present, as an example, a use case where we rely on Nonio to obtain custom compiler flags for reducing the execution time and the energy consumption of a C program, in relation to the best predetermined optimization settings provided by the compiler (e.g., -O3). (C) 2019 The Authors. Published by Elsevier B.V.

2019

Message from the symposium general chair and program chairs

Authors
Shibata, Y; Cardoso, JMP; Takamaeda Yamazaki, S;

Publication
ACM International Conference Proceeding Series

Abstract

2019

A framework for automatic and parameterizable memoization

Authors
Besnard, L; Pinto, P; Lasri, I; Bispo, J; Rohou, E; Cardoso, JMP;

Publication
SOFTWAREX

Abstract
Improving execution time and energy efficiency is needed for many applications and usually requires sophisticated code transformations and compiler optimizations. One of the optimization techniques is memoization, which saves the results of computations so that future computations with the same inputs can be avoided. In this article we present a framework that automatically applies memoization techniques to C/C++ applications. The framework is based on automatic code transformations using a source-to-source compiler and on a memoization library. With the framework users can select functions to memoize as long as they obey to certain restrictions imposed by our current memoization library. We show the use of the framework and associated memoization technique and the impact on reducing the execution time and energy consumption of four representative benchmarks. (C) 2019 The Authors. Published by Elsevier B.V.

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