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Publications

Publications by Inês Dutra

1996

Distributing And-Work and Or-Work in Parallel Logic Programming Systems

Authors
Dutra, IdC;

Publication
29th Annual Hawaii International Conference on System Sciences (HICSS-29), January 3-6, 1996, Maui, Hawaii, USA

Abstract

2003

Applying Scheduling by Edge Reversal to Constraint Partitioning

Authors
Pereira, MR; Vargas, PK; França, FMG; Castro, MCSd; Dutra, IdC;

Publication
15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2003), 10-12 November 2003, Sao Paulo, Brazil

Abstract

1999

Performance Evaluation of Or-Parallel Logic Programming Systems on Distributed Shared-Memory Architectures

Authors
Calegario, VM; Dutra, IdC;

Publication
Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31 - September 3, 1999, Proceedings

Abstract
In this work we investigate how Distributed Shared Memory (DSM) architectures affect performance of or-parallel logic programming systems and how this performance approaches that of conventional C systems. Our work concentrates on basic performance, scalability, and programmability. We use execution-driven simulation of a hardware DSM (DASH) to investigate the access patterns and caching behaviour exhibited by parallel C programs and by Aurora, a parallel logic programming system capable of exploiting implicit parallelism in Prolog programs. Aurora was originally written to run on bus-based shared-memory platforms. © Springer-Verlag Berlin Heidelberg 1999.

2005

Hierarchical submission in a Grid environment

Authors
Vargas, PK; De Castro Dutra, I; Dalto Do Nascimento, V; Santos, LAS; Da Silva, LC; Geyer, CFR; Schulze, B;

Publication
ACM International Conference Proceeding Series

Abstract
One of the challenges in grid computing research is to provide means to automatically submit, manage, and monitor applications which spread a large number of tasks. The usual way of managing these tasks is to represent each one as an explicit node in a graph, and this is the approach taken by many grid systems up to date. This approach can quickly saturate the machine where the application is launched, as we increase the number of tasks. In this work we present and validate a novel architectural model, GRAND (Grid Robust ApplicatioN Deployment), whose main objective is to deal with the problem of memory and load saturation of the submission machine. GRAND is implemented at a middleware level, aiming at providing a distributed task submission through a hierarchical organization. This paper provides an overview of the GRAND submission model as well our implementation. Initial results show that our approach can be much more effective than other approaches in the literature. Copyright 2005 ACM.

2007

Automatic constraint partitioning to speed up CLP execution

Authors
Pereira, MR; Vargas, PK; Stelling de Castro, MCS; Franca, FMG; Dutra, ID;

Publication
19TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING, PROCEEDINGS

Abstract
Speedup in distributed executions of Constraint Logic Programming (CLP) applications are directed related to a good constraint partitioning algorithm. In this work we study different mechanisms to distribute constraints to processors based on straightforward mechanisms such as Round-Robin and Block distribution, and on a more sophisticated automatic distribution method, Grouping-Sink, that takes into account the connectivity of the constraint network graph. This aims at reducing the communication overhead in distributed environments. Our results show that Grouping-Sink is, in general, the best alternative for partitioning constraints as it produces results as good or better than Round-Robin or Blocks with low communication rate.

1991

A Flexible Scheduler for the Andorra-I System

Authors
Dutra, IdC;

Publication
Parallel Execution of Logic Programs, ICLP'91 Pre-Conference Workshop, Paris, June 24, 1991, Proceedings

Abstract

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