Abstract
The evaluation of elementary functions can be performed by approximations using minimax polynomials requiring simple hardware resources. The general method to calculate an elementary function is composed by three steps: range reduction, computation of the polynomial in the reduced argument and range reconstruction. This approach allows a low-degree polynomial approximation but range reduction and reconstruction introduce a computation overhead. This work proposes an evaluation methodology without range reduction and range reconstruction steps. Applications that need to compute elementary functions may benefit from avoiding these steps if the argument belongs to a sub-domain of the function. Particularly in the context of embedded systems, applications related to digital signal processing most of the times require function evaluation within a specific interval. As a consequence of not doing range reduction, the degree of the approximant polynomials increases to maintain the required precision. Interval segmentation is an effective way to overcome this issue because the approximations are computed in smaller intervals. The proposed methodology uses non-uniform segmentation as a way to mitigate the problem arising from not carrying out range reduction. The benefits that come from applying interval segmentation to the general evaluation technique are limited by the range reduction and reconstruction steps because the segmentation only applies to the approximation step. However, when used in the proposed methodology it reveals more effective. Some elementary functions were implemented using the proposed methodology in a FPGA device. The metric used to characterize the proposed technique are the area occupation and the corresponding latency. The results of each implementation without range reduction were compared with the corresponding ones of the general method using range reduction. The results show that latency can be significantly reduced while the area is approximately the same.

Abstract
The multi-stream based automatic speech recognisers can obtain higher recognition rates than the conventional systems. This advantage is particularly evident on recognition tasks where the robustness to certain types of noise is critical, which is a very important issue in real-world applications. However most of the multi-stream based approaches remain limited to a research topic due to their higher computation complexity. The fact of this problem has not been addressed satisfactorily in the literature is the main motivation for this study. In our work we investigated the acceleration of the acoustic likelihoods computation, the most time consuming part of the whole recogniser. This paper presents results on the computational complexity of the Gaussian mixture emissions estimation in a multi-stream statistical framework. Some results concerning the recognition performance dependence on the numeric precision at different stages of that process are presented too. In order to achieve a higher acceleration of some critical computation blocks, a hardware implementation is proposed, based on the Field Programmable Gate Array (FPGA) technology.

Abstract
This paper presents a project based teaching experience in an advanced digital systems design course with emphasis on design methodologies and laboratory assignments. Projects are the core of the practised teaching methodology and are structured in a pedagogical format according to the course programme. The use of the FPGA technology as the most suitable implementation technology for digital design teaching purposes is discussed. The course structure, oriented to the development of real working digital systems, challenges the students and increases their motivation. This way, the learning process is improved and the classes are more productive. A laboratory development infrastructure based on a FPGA device, used to implement a real-time video processing system, is presented. Examples of laboratory projects implemented with this infrastructure in a recent course edition are also presented. © 2008 IEEE.

Abstract
Computer architecture is a prevalent topic of study in Informatics and Electrical Engineering courses, though students’ overall grasp of this subject’s concepts is many times hampered, mainly due to the lack of educational tools that can intuitively represent the internal behaviour of a CPU. With the evolution of the ARM architecture and its adoption in higher education institutions, the demand for this sort of tool has increased. Educational tools, specifically developed for the ARMv8 processor, are scarce and inadequate for what is necessary in an academic context. In order to contribute towards solving this problem, eduARM, a practical and interactive web platform that simulates how a ARMv8 CPU functions, was developed and is presented through this paper. Since this tool’s main purpose is to aid computer architecture students, contributing to an improvement in their learning experience, it comprises varied concepts of computer architecture and organization in a simple and intuitive manner, such as the internal structure of a CPU, in both its unicycle and pipelined versions, and the effects of executing a set of instructions. As to better understand its value, the developed tool was then validated through a case study with the participation of computer architecture students. Copyright © 2023 by SCITEPRESS – Science and Technology Publications, Lda. Under CC license (CC BY-NC-ND 4.0)