2004
Authors
Ferreira, R; Cardoso, JMP; Neto, HC;
Publication
FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS
Abstract
A wide range of reconfigurable coarse-grain architectures has been proposed in recent years, for an extensive set of applications. These architectures vary widely in the interconnectivity, number, granularity and complexity of the processing elements (PEs). The performance of a specific application usually depends heavily on the adequacy of the PEs to the particular tasks involved, but tools to efficiently experiment architectural features are lacking. This work proposes an environment for exploration and simulation of coarse-grain reconfigurable data-driven architectures. The proposed environment takes advantage of Java and XML technologies to enable a very efficient backend for experiments with different architectural trade-offs, from the array connectivity and topology to the granularity and complexity of each PE. For a proof of concept, we show results on implementing different versions of a FIR filter on a hexagonal data-driven array.
2004
Authors
Cardoso, JMP;
Publication
COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION
Abstract
This paper presents some interesting concepts of static dataflow machines that can be used by reconfigurable computing architectures. We introduce some data-driven reconfigurable arrays and summarize techniques to map imperative software programs to those architectures, some of them being focus of current research work. In particular, we briefly present a novel technique for pipelining loops. Experiments with the technique confirm important improvements over the use of conventional loop pipelining. Hence, the technique proves to be an efficient approach to map loops to coarse-grained reconfigurable architectures employing a static dataflow computational model.
2004
Authors
Cardoso, JMP; Diniz, PC;
Publication
COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION
Abstract
Loop unrolling plays an important role in compilation for Reconfigurable Processing Units (RPUs) as it exposes operator parallelism and enables other transformations (e.g., scalar replacement). Deciding when and where to apply loop unrolling, either fully or partially, leads to large design space exploration problems. In order to cope with these vast spaces, researchers have explored the application of design estimation techniques. Using estimation, tools can conduct early evaluation of the impact and interplay of transformations in both the required resources and expected performance. In this paper we present some of the current approaches and issues related to estimation of the loop unrolling impact when targeting RPUs.
2004
Authors
Bonato, V; Sanches, AK; Fernandes, MM; Cardoso, JMP; Simões, EdV; Marques, E;
Publication
ICINCO 2004, Proceedings of the First International Conference on Informatics in Control, Automation and Robotics, Setúbal, Portugal, August 25-28, 2004
Abstract
2004
Authors
Rodrigues, R; Fernandes, AR;
Publication
ICIP: 2004 INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, VOLS 1- 5
Abstract
This paper presents a robust approach for 3D point reconstruction based on a set of images taken from a static scene with known. but not necessarily exact or regular, camera parameters. The points to be reconstructed are chosen from the contours of images, and a world-based formulation of the reconstruction problem and associated epipolar geometry is used. The result is a powerful mean of transparently integrating contributions from multiple images, and increased robustness to situations such as occlusions or apparent contours. Two steps for adding robustness are proposed: cross-checking, which validates a reconstructed point taken from an image by projecting it on a special subset of the remaining images; and merging, which fuses pairs of reconstructed points that are close in 3D space and that were initially chosen from different images. Results obtained with a synthetic scene (for ground truth comparison and error assessment), and two real scenes show the improved robustness achieved with the steps proposed.
2004
Authors
Rodrigues, R; Fernandes, AR;
Publication
Proceedings of the 20th Spring Conference on Computer Graphics, SCCG '04, Budmerice, Slovakia, April 22-24, 2004
Abstract
The process of 3D reconstruction, or depth estimation, is a complex one, and many methods often have several parameters that may require fine tunning to adapt to the scene and improve reconstruction results. Usability of these methods is directly related to their response time. Epipolar geometry, a fundamental tool used in 3D reconstruction, is commonly computed on the CPU. We propose to take advantage of the advances of graphic cards, to accelerate this process. Projective texturing will be used to transfer a significant part of the computational load from the CPU into the GPU. The new approach will be illustrated in the context of a previously published work for 3D point reconstruction from a set of static images. Test results show that gains of up to two orders of magnitude in terms of computation times can be achieved, when comparing current CPU's and CPU's. We conclude that this leads to an increase in usability of 3D reconstruction methods. Copyright © 2004 by the Association for Computing Machinery, Inc.
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