Abstract
The IEC 61499 standard proposes an event driven execution model for component based (in terms of Function Blocks), distributed industrial automation applications. However, the standard provides only an informal execution semantics, thus in consequence behavior and correctness relies on the design decisions made by the tool vendor. In this paper we present the formalization of a subset of the IEC 61499 standard in order to provide an underpinning for the static verification of Function Block models by means of deductive reasoning. Specifically, we contribute by addressing verification at the component, algorithm, and ECC levels. From Function Block descriptions, enriched with formal contracts, we show that correctness of component compositions, as well as functional and transitional behavior can be ensured. Feasibility of the approach is demonstrated by manually encoding a set of representative use-cases in WhyML, for which the verification conditions are automatically derived (through the Why3 platform) and discharged (using automatic SMT-based solvers). Furthermore, we discuss opportunities and challenges towards deriving certified executables for IEC 61499 models. © 2016 IEEE.

Abstract
Complex cyber-physical systems are more and more a set of components working tightly coupled, with little or no human intervention. Assessing the correctness of these systems by testing components individually, one-by-one, is obviously not sufficient, being required to also test and validate the overall system. KhronoSim is a modular and extensible platform for testing cyber-physical systems in closed-loop, which enables the integration of simulation models and platform emulators to build a closed loop test environment. This paper presents the emulator module of KhronoSim, developed to integrate the well-known QEMU emulator in the closed-loop testing platform. © 2018 IEEE.

Abstract
This chapter describes a software architecture for processing big-data analytics considering the complete compute continuum, from the edge to the cloud. The new generation of smart systems requires processing a vast amount of diverse information from distributed data sources. The software architecture presented in this chapter addresses two main challenges. On the one hand, a new elasticity concept enables smart systems to satisfy the performance requirements of extreme-scale analytics workloads. By extending the elasticity concept (known at cloud side) across the compute continuum in a fog computing environment, combined with the usage of advanced heterogeneous hardware architectures at the edge side, the capabilities of the extreme-scale analytics can significantly increase, integrating both responsive data-in-motion and latent data-at-rest analytics into a single solution. On the other hand, the software architecture also focuses on the fulfilment of the non-functional properties inherited from smart systems, such as real-time, energy-efficiency, communication quality and security, that are of paramount importance for many application domains such as smart cities, smart mobility and smart manufacturing. © The Author(s) 2022. All rights reserved.

Abstract
Smart systems increasingly demand the processing of a massive amount of data generated by heterogeneous and distributed data sources. Due to the inherent cyber-physical nature of these systems, many applications require that this processing respects a set of non-functional requirements (such as timeliness, or energy-efficiency). To cope with this challenge, edge-cloud architectures need to provide flexible mechanisms to support varying processing needs, whilst guaranteeing the minimum level of quality of service required by these smart applications. This paper addresses this challenge in the context of the ELASTIC software architecture, which has been developed integrating responsive data-in-motion (edge computing) and latent data-at-rest analytics (cloud computing) into a single solution, satisfying extreme-scale analytics' performance requirements. The paper focuses on how the architecture fulfils the non-functional properties inherited from the applications, namely real-time and energy-efficiency, whilst ensuring the performance of the software architecture. © 2022 IEEE.

Abstract
The performance of time-predictable systems can be improved in multi-core processors using parallel programming models (e.g., OpenMP). However, schedulability analysis of parallel applications is a big challenge due to their sophisticated structure. The common drawbacks of current task-to-thread mapping approaches in OpenMP are that they (i) utilize a global queue in the mapping process, which may increase contention, (ii) do not apply heuristic techniques, which may reduce the predictability and performance of the system, and (iii) use basic analytical techniques, which may cause notable pessimism in the temporal conditions. Accordingly, this paper proposes a task-to-thread mapping method in multi-core processors based on the OpenMP framework. The mapping process is carried out through two phases: allocation and dispatching. Each thread has an allocation queue in order to minimize contention, and the allocation and dispatching processes are performed using several heuristic algorithms to enhance predictability. In the allocation phase, each task-part from the OpenMP DAG is allocated to one of the allocation queues, which includes both sibling and child task-parts. A suitable thread (i.e., allocation queue) is selected using one of the suggested heuristic allocation algorithms. In the dispatching phase, when a thread is idle, a task-part is selected from its allocation queue using one of the suggested heuristic dispatching algorithms and then dispatched to and executed by the thread. The performance of the proposed method is evaluated under different conditions (e.g., varying the number of tasks and the number of threads) in terms of application response time and overhead of the mapping process. The simulation results show that the proposed method surpasses the other methods, especially in the scenario that includes overhead of the mapping. In addition, a prototype implementation of the main heuristics is evaluated using two kernels from real-world applications, showing that the methods work better than LLVM's default scheduler in most of the configurations.

Abstract
Experts provided information about parallel and multicore systems in papers submitted and discussed at a workshop. Discussion followed about the wisdom of giving any directive further than with parallel for the programmers to control the details of how parallelism was configured, executed, and potentially mapped in the runtime. The counter argument was raised that in real-time systems there was a need for the programmer to specify such control to directly specify the behavior, which was required for behavior analysis and timing behavior analysis. Questions were raised about the memory model of the proposal, and it was decided that the general model was that which supported a shared memory system, with cache coherency and uniform access to memory= within a single partition.