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Publications

Publications by João Canas Ferreira

2016

A Precise and Hardware-Efficient Time Synchronization Method for Wearable Wired Networks

Authors
Derogarian, F; Ferreira, JC; Tavares, VMG;

Publication
IEEE SENSORS JOURNAL

Abstract
This paper presents and evaluates a high-precision, one-way, and master-to-slave time synchronization protocol to minimize the clock time skew in low-power wearable sensor networks. The protocol is implemented in the media access control layer, and is based on directly eliminating deterministic delays during transmission from source to destination node, at hardware level. The proposed protocol keeps the one-hop average synchronization error close to the signal propagation delay, and the one-hop peak-to-peak jitter equals to the period of each node's system clock period. Both values grow linearly as the hop count increases. The protocol can achieve synchronization in the range of a few nanoseconds, enough to satisfy the requirements of many applications related to wearable networks, with one-way messages. Both theoretical analysis and experimental results, in wired wearable networks, show that the proposed protocol has a better performance than precision time protocol and a standard timing protocol for both single and multi-hop situations. The proposed approach is simpler, requires no calculations, and exchanges fewer messages. Experimental results obtained with an implementation of the protocol in a 0.35-mu m CMOS technology show that this approach keeps the one-hop average clock skew around 4.6 ns and peak-to-peak skew around 50 ns for a system clock frequency of 20 mh.

2015

A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses

Authors
Paulino, N; Ferreira, JC; Cardoso, JMP;

Publication
ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS

Abstract
This article presents a reconfigurable hardware/software architecture for binary acceleration of embedded applications. A Reconfigurable Processing Unit (RPU) is used as a coprocessor of the General Purpose Processor (GPP) to accelerate the execution of repetitive instruction sequences called Megablocks. A toolchain detects Megablocks from instruction traces and generates customized RPU implementations. The implementation of Megablocks with memory accesses uses a memory-sharing mechanism to support concurrent accesses to the entire address space of the GPP's data memory. The scheduling of load/store operations and memory access handling have been optimized to minimize the latency introduced by memory accesses. The system is able to dynamically switch the execution between the GPP and the RPU when executing the original binaries of the input application. Our proof-of-concept prototype achieved geometric mean speedups of 1.60x and 1.18x for, respectively, a set of 37 benchmarks and a subset considering the 9 most complex benchmarks. With respect to a previous version of our approach, we achieved geometric mean speedup improvements from 1.22 to 1.53 for the 10 benchmarks previously used.

2015

An FPGA Framework for Genetic Algorithms: Solving the Minimum Energy Broadcast Problem

Authors
dos Santos, PV; Alves, JC; Ferreira, JC;

Publication
2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)

Abstract
Solving complex optimization problems with genetic algorithms (GAs) with custom computing architectures is a way to improve the execution time of this metaheuristic, which is known to consume considerable amounts of time to converge to final solutions. In this work, we present a scalable computing array architecture to accelerate the execution of cellular GAs (cGAs), a variant of genetic algorithms which can conveniently exploit the coarse- grain parallelism afforded by custom parallel processing. The proposed architecture targets Xilinx FPGAs and is used as an auxiliary processor of an embedded CPU (MicroBlaze). To handle different optimization problems, a high- level synthesis (HLS) design flow is proposed where the problem- dependent operations are specified in C++ and synthesised to custom hardware, thus requiring a minimum knowledge of digital design for FPGAs. The minimum energy broadcast (MEB) problem in wireless ad hoc networks is used as a case study. An existing software implementation of a GA to solve this problem is ported to the proposed computing array to demonstrate its effectiveness and the HLS- based design flow. Implementation results in a Virtex- 6 FPGA show significant speedups, while finding solutions with improved quality.

2015

Cognitive radio for SatCom applications: The screen project

Authors
Rodrigues, P; Oliveira, A; Sinogas, P; Taing, S; Eisner, J; Watts, S; Boissinot, V; Salgado, HM; Ferreira, JC; Pessoa, L; Da Silva, JM;

Publication
Proceedings of the International Astronautical Congress, IAC

Abstract
Spectrum allocation for current wireless communication systems is performed by the regulatory and licensing bodies, who allocate spectrum bands for given applications. This strict allocation severely limits the effectiveness and flexibility of the spectrum use. Cognitive radio (CR) has been demonstrated as a key emerging technology to provide flexible and efficient use of the available spectrum by allocating frequency bands dynamically, and to improve the performance of radio systems in congested or jammed environments. Frequencies that are reserved or usually occupied can be exploited if the cognitive radio system identifies them as being free. Such a system is also able to monitor and deal with degrading communication performance or regulatory constraints. It automatically adjusts radio settings to use the best wireless channels in its environment, ensuring appropriate quality of service, efficiency and versatility. The SCREEN project proposes to extend the concept of cognitive radio to space and particularly to SatCom applications. This is an on-going project funded by the Horizon 2020 European Union programme. CR has never been used or tested in space, since previous research has been focused in terrestrial technologies. By addressing this topic and demonstrating its capabilities and benefits for space applications, SCREEN will contribute to a better management of this scarce resource that is bandwidth. While it has already been demonstrated that CR technology radically improves the performance for terrestrial applications at many different levels, the same benefits also apply in Space and especially in the SatCom segment, where the services provided need to ensure quality to the clients, for market competitiveness. CR has the potential to enable different approaches for managing the growing satellite communication demands and provides flexibility to explore new types of hybrid networks. SatCom operators will benefit from having the flexibility to allocate frequency slots dynamically, according to the instantaneous traffic patterns, instead of reserving fixed bands within regulatory constraints. Additionally, by optimising the spectrum management, SatCom operators can accommodate more users at the same time, without sacrificing the network performance. In this paper we will describe the overall concept behind the SCREEN project and present the results of a complete framework analysis, consisting of technical conclusions, market and impact analyses, regulatory considerations/constraints and requirements. Based on this analysis we further present functional, performance and test requirements for the project, which will show the project direction and outcome, together with the expected benefits that this technology will bring to Space applications. Copyright

2016

Dynamically Reconfigurable FFT Processor for Flexible OFDM Baseband Processing

Authors
Ferreira, ML; Barahimi, A; Ferreira, JAC;

Publication
2016 11TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA (DTIS)

Abstract
The Physical layer architectures for the next generation of wireless devices will be characterized by a high degree of flexibility for real-time adaptation to communication conditions variability. OFDM-based architectures are strong candidates for the Physical layer implementation in 5G systems and one of the most important baseband processing operations required by this waveform is the Fast Fourier Transform (FFT). This paper proposes a dynamically reconfigurable FFT processor supporting FFT sizes and throughputs required by the most widely used wireless standards. The FFT reconfiguration was achieved by means of FPGA-based Dynamic Partial Reconfiguration (DPR) techniques, which enables run-time FFT size adaptation according to communication requirements and better resource utilization. The impact of DPR in terms of reconfiguration time and power consumption overhead was evaluated. The obtained results encourage the exploitation of DPR techniques to implement reconfigurable hardware infrastructures for OFDM baseband processing engines.

2016

Dynamically Reconfigurable LTE-compliant OFDM Modulator for Downlink Transmission

Authors
Ferreira, ML; Barahimi, A; Ferreira, JC;

Publication
2016 CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS 2016)

Abstract
As the number of wireless devices, services, communication standards and respective modes of operation rapidly grows, the design of reconfigurable digital baseband processing systems for radio devices becomes more important and challenging. Long Term Evolution (LTE) is among the most relevant wireless systems in 4G communications and its waveform is OFDM-based. According to the LTE mode of operation, OFDM parameters may change and influence baseband processing operations. This paper presents a dynamically reconfigurable LTE-compliant OFDM modulator for Downlink transmission able to adapt its internal hardware organization on-demand according to the digital modulation scheme and OFDM parameters, such as number of data subcarriers, IFFT size, Cyclic Prefix and window length. System reconfiguration is performed by employing FPGA-based Dynamic Partial Reconfiguration (DPR) techniques. The worst-case DPR latencies measured are 895 mu s and 1.192 ms for digital modulation and channel bandwidth adaptation, respectively. These results show that the adopted design approach is feasible in wireless baseband processing systems. Power estimations suggest that circuit specialization at run-time can potentially improve system power efficiency.

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