Carvalho, G; Ferreira, JC; Tavares, VG;
2020 XXXV CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS)
Typical analogue-to-digital conversion (ADC) architectures, at Nyquist rate, tend to occupy a big portion of the integrated circuit die area and to consume more power than desired. Recently, with the rise of Interet-of-Things (IoT), there is a high demand for architectures that can have both reduced area and power consumption. Time encoding machines (TEM) might be a promising alternative. These types of encoders result in very simple and low-power analogue circuits, shifting most of its complexity to the decoding stage, typically stationed in a place with access to more resources. This paper focuses on a particular TEM, the integrate-and-fire neuron (IFN). The IFN modulation is based on a simplified first-order model of neural operation and it encodes the signal in a very power efficient manner. In the end, a novel hardware architecture for the reconstruction of the IFN encoded signal based on a spiking model will be presented. The method is demonstrated and implemented on FPGA, reaching an ENOB as high as 8.23.
Carvalho, G; Pereira, M; Kiazadeh, A; Tavares, VG;
Resistive switching behaviour has been demonstrated to be a common characteristic to many materials. In this regard, research teams to date have produced a plethora of different devices exhibiting diverse behaviour, but when system design is considered, finding a 'one-model-fits-all' solution can be quite difficult, or even impossible. However, it is in the interest of the community to achieve more general modelling tools for design that allows a quick model update as devices evolve. Laying the grounds with such a principle, this paper presents an artificial neural network learning approach to resistive switching modelling. The efficacy of the method is demonstrated firstly with two simulated devices and secondly with a 4 mu m(2) amorphous IGZO device. For the amorphous IGZO device, a normalized root-mean-squared error (NRMSE) of 5.66 x 10(-3) is achieved with a [2, 50,50 ,1] network structure, representing a good balance between model complexity and accuracy. A brief study on the number of hidden layers and neurons and its effect on network performance is also conducted with the best NRMSE reported at 4.63 x 10(-3). The low error rate achieved in both simulated and real-world devices is a good indicator that the presented approach is flexible and can suit multiple device types.
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