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Publications

Publications by CTM

2020

Improving performance and energy consumption in embedded systems via binary acceleration: A survey

Authors
Paulin, N; Ferreira, JC; Cardoso, JMP;

Publication
ACM Computing Surveys

Abstract
The breakdown of Dennard scaling has resulted in a decade-long stall of the maximum operating clock frequencies of processors. To mitigate this issue, computing shifted to multi-core devices. This introduced the need for programming flows and tools that facilitate the expression of workload parallelism at high abstraction levels. However, not all workloads are easily parallelizable, and the minor improvements to processor cores have not significantly increased single-threaded performance. Simultaneously, Instruction Level Parallelism in applications is considerably underexplored. This article reviews notable approaches that focus on exploiting this potential parallelism via automatic generation of specialized hardware from binary code. Although research on this topic spans over more than 20 years, automatic acceleration of software via translation to hardware has gained new importance with the recent trend toward reconfigurable heterogeneous platforms. We characterize this kind of binary acceleration approach and the accelerator architectures on which it relies. We summarize notable state-of-the-art approaches individually and present a taxonomy and comparison. Performance gains from 2.6× to 5.6× are reported, mostly considering bare-metal embedded applications, along with power consumption reductions between 1.3× and 3.9×. We believe the methodologies and results achievable by automatic hardware generation approaches are promising in the context of emergent reconfigurable devices. © 2020 Association for Computing Machinery.

2020

A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems

Authors
Derogarian Miyandoab, FD; Canas Ferreira, JC; Grade Tavares, VMG; Machado da Silva, JM; Velez, FJ;

Publication
IEEE/ACM Transactions on Networking

Abstract

2020

Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets

Authors
Paulino, N; Ferreira, JC; Cardoso, JMP;

Publication
IEEE Access

Abstract

2020

Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework

Authors
Paulino, N; Ferreira, JC; Bispo, J; Cardoso, JMP;

Publication
30th International Conference on Field-Programmable Logic and Applications, FPL 2020, Gothenburg, Sweden, August 31 - September 4, 2020

Abstract

2020

Flexible Baseband Modulator Architecture for Multi-Waveform 5G Communications

Authors
Lopes Ferreira, M; Canas Ferreira, J;

Publication
Field Programmable Gate Arrays (FPGAs) II

Abstract

2020

Hardware architecture for integrate-and-fire signal reconstruction on FPGA

Authors
Carvalho, G; Ferreira, JC; Tavares, VG;

Publication
2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)

Abstract

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