Cookies Policy
We use cookies to improve our site and your experience. By continuing to browse our site you accept our cookie policy. Find out More
Close
  • Menu
Publications

Publications by CTM

2018

BMOG: boosted Gaussian Mixture Model with controlled complexity for background subtraction

Authors
Martins, I; Carvalho, P; Corte Real, L; Alba Castro, JL;

Publication
Pattern Analysis and Applications

Abstract

2018

Experimental Evaluation of Resonant Tunnelling Diode Oscillators Employing Advanced Modulation Formats

Authors
Tavares, JS; Pessoa, LM; Salgado, HM;

Publication
International Conference on Transparent Optical Networks

Abstract
The performance of Resonant Tunnelling Diode (RTD) oscillators with an optical window is evaluated experimentally, in the transmission of advanced modulation formats using electrical and optical modulation, for the first time. Additionally, the impact of phase noise in the transmission performance is also assessed. © 2018 IEEE.

2018

An FPGA array for cellular genetic algorithms: Application to the minimum energy broadcast problem

Authors
dos Santos, PV; Alves, JC; Ferreira, JC;

Publication
Microprocessors and Microsystems

Abstract
The genetic algorithm is a general purpose optimization metaheuristic for solving complex optimization problems. Because the algorithm usually requires a large number of iterations to evolve a population of solutions to good final solutions, it normally exhibits long execution times, especially if running on low-performance conventional processors. In this work, we present a scalable computing array to parallelize and accelerate the execution of cellular GAs (cGAs). This is a variant of genetic algorithms which can conveniently exploit the coarse-grain parallelism afforded by custom parallel processing. The proposed architecture targets Xilinx FPGAs and was implemented as an auxiliary processor of an embedded soft-core CPU (MicroBlaze). To facilitate the customization for different optimization problems, a high-level synthesis design flow is proposed where the problem-dependent operations are specified in C++ and synthesised to custom hardware, thus demanding of the programmer only minimal knowledge of low-level digital design for FPGAs. To demonstrate the efficiency of the array processor architecture and the effectiveness of the design methodology, the development of a hardware solver for the minimum energy broadcast problem in wireless ad hoc networks is employed as a use case. Implementation results for a Virtex-6 FPGA show significant speedups, especially when comparing to embedded processors used in current FPGA devices. © 2018

2018

A parallel-pipelined OFDM baseband modulator with dynamic frequency scaling for 5G systems

Authors
Ferreira, ML; Ferreira, JC; Hübner, M;

Publication
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Abstract
5G heterogeneity will cover a huge diversity of use cases, ranging from enhanced-broadband to low-throughput and low-power communications. To address such requirements variety, this paper proposes a parallel-pipelined architecture for an OFDM baseband modulator with clock frequency run-time adaptation through dynamic frequency scaling (DFS). It supports a set of OFDM numerologies recently proposed for 5G communication systems. The parallel-pipelined architecture can achieve high throughputs at low clock frequencies (up to 520.3 MSamples/s at 160 MHz) and DFS allows for the adjustment of baseband processing clock frequency according to immediate throughput demands. The application of DFS increases the system’s power efficiency by allowing power savings up to 62.5%; the resource and latency overhead is negligible. © Springer International Publishing AG, part of Springer Nature 2018.

2018

Flexible and Dynamically Reconfigurable FPGA-Based FS-FBMC Baseband Modulator

Authors
Ferreira, ML; Ferreira, JC;

Publication
2018 IEEE International Symposium on Circuits and Systems (ISCAS)

Abstract

2018

Dynamic Partial Reconfiguration of Customized Single-Row Accelerators

Authors
Paulino, NMC; Ferreira, JC; Cardoso, JMP;

Publication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Abstract

  • 1
  • 218