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Publications

Publications by CTM

2020

Efficient CIEDE2000-based Color Similarity Decision for Computer Vision

Authors
Pereira, A; Carvalho, P; Coelho, G; Corte Real, L;

Publication
IEEE Transactions on Circuits and Systems for Video Technology

Abstract

2020

Texture collinearity foreground segmentation for night videos

Authors
Martins, I; Carvalho, P; Corte Real, L; Alba Castro, JL;

Publication
Computer Vision and Image Understanding

Abstract
One of the most difficult scenarios for unsupervised segmentation of moving objects is found in nighttime videos where the main challenges are the poor illumination conditions resulting in low-visibility of objects, very strong lights, surface-reflected light, a great variance of light intensity, sudden illumination changes, hard shadows, camouflaged objects, and noise. This paper proposes a novel method, coined COLBMOG (COLlinearity Boosted MOG), devised specifically for the foreground segmentation in nighttime videos, that shows the ability to overcome some of the limitations of state-of-the-art methods and still perform well in daytime scenarios. It is a texture-based classification method, using local texture modeling, complemented by a color-based classification method. The local texture at the pixel neighborhood is modeled as an N-dimensional vector. For a given pixel, the classification is based on the collinearity between this feature in the input frame and the reference background frame. For this purpose, a multimodal temporal model of the collinearity between texture vectors of background pixels is maintained. COLBMOG was objectively evaluated using the ChangeDetection.net (CDnet) 2014, Night Videos category, benchmark. COLBMOG ranks first among all the unsupervised methods. A detailed analysis of the results revealed the superior performance of the proposed method compared to the best performing state-of-the-art methods in this category, particularly evident in the presence of the most complex situations where all the algorithms tend to fail. © 2020 Elsevier Inc.

2020

Patch antenna-in-package for 5G communications with dual polarization and high isolation

Authors
Santos, H; Pinho, P; Salgado, H;

Publication
Electronics (Switzerland)

Abstract
In this paper, we describe the design of a dual polarized packaged patch antenna for 5G communications with improved isolation and bandwidth for K-band. We introduce a differential feeding technique and a heuristic-based design of a matching network applied to a single layer patch antenna with parasitic elements. This approach resulted in broader bandwidth, reduced layer count, improved isolation and radiation pattern stability. The results were validated through finite element method (FEM) and method of moments (MoM) simulations. A peak gain of 5 dBi, isolation above 40 dB and a radiation efficiency of 60% were obtained. © 2020 by the authors. Licensee MDPI, Basel, Switzerland.

2020

Design of an Anechoic Chamber for W-Band and mmWave

Authors
Pinho, P; Santos, H; Salgado, H;

Publication
ELECTRONICS

Abstract
In this paper, we describe the design of an electrically large anechoic chamber for usage on millimetre-wave bands. Ansys Savant sotware was used to perform a simulation of the chamber, using physical optics coupled with uniform theory of diffraction (PO/UTD). Moreover, a method based on an open waveguide probe is described in this paper to obtain the electrical properties of the RF absorbers at millimetre-wave frequencies. Two different source antennas were simulated in this work and the corresponding quiet zones predicted. The largest quiet zone was 30 mm x 30 mm x 50mm, for a chamber size of 1.2 m x 0.6 m x 0.6 m.

2020

A Dynamically Reconfigurable Dual-Waveform Baseband Modulator for Flexible Wireless Communications

Authors
Ferreira, ML; Ferreira, JC;

Publication
JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY

Abstract
In future wireless communication systems, several radio access technologies will coexist and interwork to provide a great variety of services with different requirements. Thus, the design of flexible and reconfigurable hardware is a relevant topic in wireless communications. The combination of high performance, programmability and flexibility makes Field-programmable gate array a convenient platform to design such systems, especially for base stations. This paper describes a dynamically reconfigurable baseband modulator for Orthogonal Frequency Division Multiplexing and Filter-bank Multicarrier modulation waveforms implemented on a Virtex-7 board. The design features Dynamic Partial Reconfiguration (DPR) capabilities to adapt its mode of operation at run-time and is compared with a functionally equivalent static multi-mode design regarding processing throughput, resource utilization, functional density and power consumption. The DPR-based design implementation reserves about half the resources used by static multi-mode counterpart. Consequently, the baseband processing dynamic power consumption observed in the DPR-based design is between 26 mW to 90 mW lower than in the static multi-mode design, representing a dynamic power reduction between 13% to 52%. The worst-case DPR latency measured was 1.051 ms, while the DPR energy overhead is below 1.5 mJ. Considering latency requirements for modern wireless standards and power consumption constraints for commercial base stations, the DPR application is shown to be valuable in multi-standard and multi-mode systems, as well as in scenarios such as multiple-input and multiple-output or dynamic spectrum aggregation.

2020

Parallel Implementation of K-Means Algorithm on FPGA

Authors
Dias, LA; Ferreira, JC; Fernandes, MAC;

Publication
IEEE ACCESS

Abstract
The K-means algorithm is widely used to find correlations between data in different application domains. However, given the massive amount of data stored, known as Big Data, the need for high-speed processing to analyze data has become even more critical, especially for real-time applications. A solution that has been adopted to increase the processing speed is the use of parallel implementations on FPGA, which has proved to be more efficient than sequential systems. Hence, this paper proposes a fully parallel implementation of the K-means algorithm on FPGA to optimize the system & x2019;s processing time, thus enabling real-time applications. This proposal, unlike most implementations proposed in the literature, even parallel ones, do not have sequential steps, a limiting factor of processing speed. Results related to processing time (or throughput) and FPGA area occupancy (or hardware resources) were analyzed for different parameters, reaching performances higher than 53 millions of data points processed per second. Comparisons to the state of the art are also presented, showing speedups of more than over a partially serial implementation.

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