Abstract
This paper describes the design of a processor specific for testing cores embedded in system-on-chip. This processor which can be implemented within a system's reconfigurable area, shall be responsible for scheduling and control test operations and perform preliminary data processing, as well as to provide the interface with an external tester Building these test operations on-chip allows for simplifying external tester interface and to reduce testing time. The testing procedure and the infrastructure required to test an AID converter is described as an example.

Abstract

Abstract
Next generation communication networks will be characterized by the coexistence of multiple technologies and user devices in an integrated fashion. The increasing number of devices owned by a single user will lead to a new communication paradigm: users owning multiple devices that form cooperative networks, and networks of different users that communicate with each other, e.g., acquiring Internet access through each other. In this communication scenario no user intervention should be required and technology should seamlessly adapt to the user's context, preferences, and needs. In this paper we address one of those scenarios, interworking between Personal Area Networks, using legacy technologies and the Ambient Network and Network Composition concepts, herein explained. We argue that new functionalities should be introduced to enable effortless use of legacy technologies in such dynamic and heterogeneous environments. © 2005 IEEE.

Abstract

Abstract

Abstract
A simple splice technique to fuse a SMF-28 (TM) and a microstructured fibre using a conventional electric-are splicer is presented. The technique consists in applying the electric arc in the SMF-28 (TM) region. The fusion-loss dependence with arc duration for constant fusion power is also investigated. A splice loss of 0.25 dB is obtained with high rtproducibility. (c) 2005 Wiley Periodicals, Inc.