Abstract
We have investigated the polarization properties of long-period fibre gratings fabricated using the electric arc technique. It was found that the choice of the fabrication parameters (electric current, arc duration and pulling tension) affects the polarization dependent loss of the produced gratings. In particular, a non-monotonic dependence on the external pulling tension was obtained.

Abstract
The underlying formation mechanisms and the properties of long-period gratings produced through arc discharges are intrinsically related to the temperature reached by the fibre during arc exposure. In this work, the determination of the fibre temperature was based on Plank's blackbody radiation law. The radiation emitted by the optical fibre during heating due to an electric arc discharge, detected using a Cronin spectrometer, was fitted to the emission spectrum of the blackbody radiation, allowing the estimation of the temperature range attained by the fibre. A peak temperature of 1400 +/- 50 degrees C was obtained.

Abstract
We have investigated the sensitivity of arc-induced long-period gratings to changes of ambient refractive index. Two pure-silica-core fibres with different cladding diameters and a standard fibre were used in this study. For a 6 x 10(-3) change of the refractive index, a 240 pm shift of the resonant wavelength was achieved with long-period gratings written in the 125 mu m cladding diameter pure-silica-core fibre.

Abstract
All-optical switching devices based on fibre Bragg grating (FBG) structures written on a standard single-mode fibre and in an erbium-doped fibre have been experimentally demonstrated in the third telecommunication window. The switching devices work due to the thermal changes induced by a high-power continuous-wave laser diode. The filters tunability characteristics have been demonstrated for different pump powers (up to 900 mW) and different pump laser wavelengths (at 980 and 1480 nm), presenting different thermal absorption behaviour within different working regimes. (c) 2006 Wiley Periodicals, Inc.

Abstract
The effective use of dynamic reconfiguration requires the designer to address many implementation issues. The market introduction of feature-full platform FPGAs equipped with embedded CPU blocks expands the number of situations where dynamic reconfiguration may be applied to improve overall performance and logic utilization. The paper compares the design of two similar systems supporting dynamic reconfiguration and the issues that were addressed in their implementation. The first system supports 32-bit data transfers between CPU and the dynamically reconfigurable circuits. The other implementation supports 64-bit transfers, but its effective use is more complicated and several restrictions must be taken into account. The work includes a performance comparison of the two designs on several simple tasks, including pattern matching, image processing and hashing. © 2006 IEEE.

Abstract
Run-time partial reconfiguration of programmable hardware devices can be applied to enhance many applications in high-end embedded systems, particularly those that employ recent platform FPGAs. The effective use of this approach is often hampered by the complexity added to the system development process and by limited tool support. The paper is concerned with several aspects related to the effective exploitation of run-time partial reconfiguration, with particular emphasis on the generation of partial configurations and the run-time utilisation of the reconfigurable resources. The paper presents an approach inspired by the traditional software development: partial configurations are produced by assembling components from a previously created library, thus enabling the embedded application developer to produce the configuration data required for run-time modifications with less effort than is needed with the conventional design flow. A tool that supports this approach is also described. A second set of issues is addressed by a run-time support library that provides facilities for managing the hardware reconfiguration process and the communication with the reconfigured circuits. The use of run-time partial reconfiguration requires a high level of system support. The paper describes one possible approach, presenting a demonstration system developed to support the present work and characterising its performance. In order to clarify the advantages of the approach to run-time reconfigiaration discussed in the paper, two small case studies are described, the first on the use of dedicated datapaths for subword operations and the second on two-dimensional pattern-matching for bilevel images. Timing measurements for both cases are included.