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Publications

Publications by CTM

2013

LoCoBoard: Low-Cost Interactive Whiteboard Using Computer Vision Algorithms

Authors
Soares, C; Moreira, RS; Torres, JM; Sobral, P;

Publication
ISRN Machine Vision

Abstract

2013

High-Gain Topologies for Transparent Electronics

Authors
Bahubalindruni, P; Tavares, VG; Barquinha, P; Martins, R; Fortunato, E;

Publication
2013 IEEE EUROCON

Abstract
Transparent TFT technologies, with amorphous semiconductor oxides are lacking a complementary type transistor. This represents a real challenge, when the design of high-gain amplifiers are considered, without resorting to passive resistive elements. However, some solutions do exist to overcome the lack of a p-type transistor. This paper then presents a comparison analysis of two high-gain single-stage amplifier topologies using only n-type enhancement transistors. In these circuits, high gain is achieved using positive feedback for the load impedance. The comparison is carried out in terms of bandwidth, power consumption and complexity under identical bias conditions. Further, the same load impedance is used to develop a novel high-gain multiplier. All the circuits are simulated using a 0.35 mu m CMOS technology, as it is easy to test the reliability of the methods, since CMOS transistors have trustworthy models.

2013

Transparent Current Mirrors With a-GIZO TFTs: Neural Modeling, Simulation and Fabrication

Authors
Bahubalindruni, PG; Tavares, VG; Barquinha, P; Duarte, C; de Oliveira, PG; Martins, R; Fortunato, E;

Publication
JOURNAL OF DISPLAY TECHNOLOGY

Abstract
This paper characterizes transparent current mirrors with n-type amorphous gallium-indium-zinc-oxide (a-GIZO) thin-film transistors (TFTs). Two-TFT current mirrors with different mirroring ratios and a cascode topology are considered. A neural model is developed based on the measured data of the TFTs and is implemented in Verilog-A; then it is used to simulate the circuits with Cadence Virtuoso Spectre simulator. The simulation outcomes are validated with the fabricated circuit response. These results show that the neural network can model TFT accurately, as well as the current mirroring ability of the TFTs.

2013

High-gain Amplifier with n-type Transistors

Authors
Bahubalindruni, P; Tavares, VG; de Oliveira, PG; Barquinha, P; Martins, R; Fortunato, E;

Publication
2013 IEEE INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)

Abstract
A high-gain amplifier topology, with all single n-type enhancement transistors, is proposed in this paper. This type of circuits are essential in transparent TFT technologies, such as GIZO and ZnO that lack complementary type transistor. All circuits were simulated using BSIM3V3 model of a 0.35 mu m CMOS technology, due to the absence of a complete electrical model for the TFTs. Results reveal that the proposed circuit promise more gain, lower power consumption and higher bandwidth than the existing solutions under identical bias conditions.

2013

An Adaptive Duty-Cycle Methodology for PV Power Maximization Using a Single Variable

Authors
Vidal, AA; Tavares, VG; Principe, JC;

Publication
2013 IEEE EUROCON

Abstract
This paper presents a new methodology to maximize the power output of Photovoltaic panels (PV), based on an adaptive duty-cycle methodology. The approach embeds the DC/DC converter characteristic in the cost function, allowing an optimization based on a single measured variable. Two cost functions, and respective learning rules, are derived. The first, more complex and comprehensive, traces the ground for the second which is less computational intensive and solves stability issues and implementation difficulties. It is also demonstrated that the system is asymptotically stable around the optimum duty-cycle, in the Lyapunov sense. Both methods are compared through simulations and deviations from the optimal solution are assessed.

2013

Predicting Short 802.11 Sessions from RADIUS Usage Data

Authors
Allandadi, A; Morla, R; Aguiart, A; Cardoso, JS;

Publication
PROCEEDINGS OF THE 2013 38TH ANNUAL IEEE CONFERENCE ON LOCAL COMPUTER NETWORKS WORKSHOPS (LCN WORKSHOPS)

Abstract
The duration of 802.11 user sessions has been widely studied in the context of analyzing user behavior and mobility. Short (smaller-than-5-minutes) sessions are never used or characterized in these analyses as they are unrelated to user behavior and considered as artifacts introduced by the wireless network. In this paper we characterize short 802.11 sessions as recorded through RADIUS authentication. We show that 50% of access points have 70% of smaller than 5 minutes sessions in a 5 months trace from the Eduroam academic wireless network in the University of Porto. Exactly because they are artifacts introduced by the network, short sessions are an important indicator for network management and the quality of the wireless access. Network managers typically do not collect and process session information but rely on SNMP to provide summaries of 802.11 usage data. We develop a modeling framework to provide predictions for the number of short sessions from SNMP data. We model the data stream of each access point using two methods of regression and one classification technique. We evaluate these models based on short session prediction accuracy. The models are trained on the 5 months data and the best results show prediction accuracy of 95.27% in polynomial regression at degree of 3.

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