2014
Authors
Otebolaku, AM; Andrade, MT;
Publication
2014 28TH INTERNATIONAL CONFERENCE ON ADVANCED INFORMATION NETWORKING AND APPLICATIONS WORKSHOPS (WAINA)
Abstract
Current solutions for delivering adapted multimedia content in mobile environments take into account only a limited set of contextual information, and can be regarded as passive solutions. We propose a new solution that anticipates user's needs based on the contexts of use and preferences to deliver media content to mobile users. This paper describes the profiling approach of the proposed solution, and a context-aware content-based recommendation for smart devices. Recommendations are issued based on user history, driven by real-time contextual conditions.
2014
Authors
Otebolaku, AM; Andrade, MT;
Publication
Lecture Notes in Electrical Engineering
Abstract
The incredible appeals of smartphones and the unprecedented progress in the development of mobile and wireless networks in recent years have enabled ubiquitous availability of myriad media contents. Consequently, it has become problematic for mobile users to find relevant media items. However, context awareness has been proposed as a means to help mobile users find relevant media items anywhere and at any time. The contribution of this paper is the presentation of a context-aware media recommendation framework for smart devices (CAMR). CAMR supports the integration of context sensing, recognition, and inference, using classification algorithms, an ontology-based context model and user preferences to provide contextually relevant media items to smart device users. This paper describes CAMR and its components, and demonstrates its use to develop a context-aware mobile movie recommendation on Android smart devices. Experimental evaluations of the framework, via an experimental context-aware mobile recommendation application, confirm that the framework is effective, and that its power consumption is within acceptable range. © 2014 Springer International Publishing Switzerland.
2014
Authors
Catarino, A; Rocha, AM; Abreu, MJ; Derogarian, F; Da Silva, J; Ferreira, J; Tavares, V; Correia, M; Dias, R;
Publication
Journal of Textile Engineering
Abstract
Human motion capture systems help clinicians to detect and identify mobility impairments, early stages of pathologies and evaluate the effectiveness of surgical or rehabilitation intervention. Although there is a considerable number of solutions presently available, these systems are often expensive, complex, difficult to wear, and uncomfortable for the patient. With the purpose of solving the formerly mentioned problems, a new wearable locomotion data capture system for gait analysis is being developed. This system will allow the measurement of several locomotion-related parameters in a practical and non-invasive way, also reusable, that can be used by patients from light to severe impairments or disabilities. © 2013 The Textile Machinery Society of Japan.
2014
Authors
Derogarian, F; Ferreira, JC; Grade Tavares, VMG;
Publication
2014 17TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD)
Abstract
This paper describes and evaluates a fully digital circuit for one-way master-to-slave highly precise time synchronization in a low-power, wearable system equipped with a set of sensor nodes connected in a mesh network. Sensors are connected to each other with conductive yarns that are used as one-wire bidirectional communication links. The circuit is designed to perform synchronization in the Medium Access Control (MAC) layer. In each sensor node, the synchronization circuit provides a synchronized, programmable clock signal and a real-time counter for time stamping. Experimental results obtained with an implementation in 0.35 mu m CMOS technology for a network of electromyography sensors show that the circuit keeps the one-hop average clock skew below 4.6 ns, a value small enough to satisfy many wearable application requirements.
2014
Authors
Paulino, N; Ferreira, JC; Cardoso, JMP;
Publication
2014 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING WITH APPLICATIONS (ISPA)
Abstract
This paper presents a binary acceleration approach based on extending a General Purpose Processor (GPP) with a Reconfigurable Processing Unit (RPU), both sharing an external data memory. In this approach repeating sequences of GPP instructions are migrated to the RPU. The RPU resources are selected and organized off-line using execution trace information. The RPU core is composed of Functional Units (FUs) that correspond to single CPU instructions. The FUs are arranged in stages of mutually independent operations. The RPU can enable several stages in tandem, depending on the data dependencies. External data memory accesses are handled by a configurable dual-port cache. A prototype implementation of the architecture on a Spartan-6 FPGA was validated with 12 benchmarks and achieved an overall geometric mean speedup of 1.91x.
2014
Authors
Derogarian, F; Ferreira, JC; Grade Tavares, VMG;
Publication
2014 IEEE 23RD INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS (ISIE)
Abstract
This paper presents a network router and transceiver for wearable, low-power, high-speed Body Area Networks (BAN) applications running in a mesh network of sensors embedded in textiles and connected to each other with conductive yarns functioning as bidirectional transmission channels. The routing of data packets from sensor nodes to a sink node is based on hybrid circuit and packet switching. In comparison with pure packet switching, hybrid routing decreases end-to-end delay, power consumption and buffer size. The proposed design uses independent sender, receiver and circuit switching modules, thereby allowing the nodes to simultaneously send and receive data. The simulation results show that circuit and hybrid switching modes significantly increase the performance of the system. In addition, implementing the complete packet process on FPGA, instead of using an external microcontroller as in previous work, enables a much faster routing process. The results are based on a Verilog description of the system, which has been synthesized for a low-power IGLOO FPGA with Libero Project Manager and simulated with ModelSim. The implementation operates successfully at a data rate of 20 Mbps.
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