Abstract
This letter presents a novel high-gain four-quadrant analog multiplier using only n-type enhancement indium-gallium-zinc-oxide thin-film-transistors. The proposed circuit improves the gain by using an active load with positive feedback. A Gilbert cell with a diode-connected load is also presented for comparison purposes. Both circuits were fabricated on glass at low temperature (200 degrees C) and were successfully characterized at room temperature under normal ambient conditions, with a power supply of 15 V and 4-pF capacitive load. The novel circuit has shown a gain improvement of 7.2 dB over the Gilbert cell with the diode-connected load. Static linearity response, total harmonic distortion, frequency response, and power consumption are reported. This circuit is an important signal processing building block in large-area sensing and readout systems, specially if data communication is involved.

Abstract
Security is becoming an essential problem for integrated circuits (ICs). Various attacks, such as reverse engineering and dumping on-chip data, have been reported to undermine IC security. IEEE 1149.1, also known as JTAG, is primarily used for IC manufacturing test but inevitably provides a "backdoor" that can be exploited to attack ICs. Encryption has been used extensively as an effective mean to protect ICs through authentication, but a few weaknesses subsist, such as key leakage. Signature-based techniques ensure security using a database that includes known attacks, but fail to detect attacks that are not contained by the database. To overcome these drawbacks, a two-layer learning-based protection scheme is proposed. Specifically, the scheme monitors the execution of JTAG instructions and uses support vector machines (SVM) to identify abnormal instruction sequences. The use of machine learning enables the detection of unseen attacks without the need for key-based authentication. The experiments based on the OpenSPARC T2 platform demonstrate that the proposed scheme improves the accuracy of detecting unseen attacks by 50% on average when compared to previous work.

Abstract
This paper presents a study concerning the role of channel length scaling on IGZO TFT technology benchmark parameters, which are fabricated at temperatures not exceeding 180 degrees C. The parameters under investigation are unity current-gain cutoff frequency, intrinsic voltage-gain, and on-resistance of the bottom-gate IGZOTFTs. As the channel length varies from 160 to 3 mu m, the measured cutoff frequency increases from 163 kHz to 111.5 MHz, which is a superior value compared to the other competing low-temperature thin-film technologies, such as organic TFTs. On the other hand, for the same transistor dimensions, the measured intrinsic voltage-gain is changing from 165 to 5.3 and the on-resistance is decreasing from 1135.6 to 26.1 k Omega. TFTs with smaller channel length (3 mu m) have shown a highly negative turn-on voltage and hump in the subthreshold region, which can be attributed to short channel effects. The results obtained here, together with their interpretation based on device physics, provide crucial information for accurate IC design, enabling an adequate selection of device dimensions to maximize the performance of different circuit building blocks assuring the multifunctionality demanded by system-on-panel concepts.

Abstract
This paper presents a behavioral model for amorphous indium-gallium-zinc oxide thin-film transistor using artificial neural network (ANN) based equivalent circuit (EC) approach to predict static and dynamic behavior of the device. In addition, TFT parasitic capacitances (C-GS and C-GD) characterization through measurements is also reported. In the proposed model, an EC is derived from the device structure, in terms of electrical lumped elements. Each electrical element in the EC is modeled with an ANN. Then these ANNs are connected together as per the EC and implemented in Verilog-A. The proposed model performance is validated by comparing the circuit simulation results with the measured response of a simple common-source amplifier, which has shown 12.2 dB gain, 50 mu W power consumption and 85 kHz 3-dB frequency with a power supply of 6 V. The same circuit is tested as an inverter and its response is also presented up to 50 kHz, from both simulations and measurements. These results show that the model is capable of capturing both small and large signal behavior of the device to good accuracy, even including the harmonic distortion of the signal (that emphasizes the nonlinear behavior of the parasitic capacitance), making the model suitable for IC design.

Abstract
This paper presents the characterization of fundamental analog and digital circuits with a-IGZO TFTs from measurements performed at normal ambient. The fundamental blocks considered in this work include digital logic gates, a low power single stage high-gain amplifier with capcacitive bootstrapping and a level shifter/buffer. These circuits are important functional blocks in analog/Mixed signal IC design with oxide TFTs. Being fabricated at low temperature (<200 degrees C), they can find potential applications in low-cost large-area flexible systems.

Abstract
A novel linear analog adder is proposed only with n-type enhancement IGZO TFTs that computes summation of four voltage signals. However, this design can be easily extended to perform summation of higher number of signals, just by adding a single TFT for each additional signal in the input block. The circuit needs few number of transistors, only a single power supply irrespective of the number of voltage signals to be added, and offers good accuracy over a reasonable range of input values. The circuit was fabricated on glass substrate with the annealing temperature not exceeding 200 degrees C. The circuit performance is characterized from measurements under normal ambient at room temperature, with a power supply voltage of 12 V and a load of approximate to 4pF. The designed circuit has shown a linearity error of 2.3% (until input signal peak to peak value is 2 V), a power consumption of 78 mu W and a bandwidth of approximate to 115 kHz, under the worst case condition (when it is adding four signals with the same frequency). In this test setup, it has been noticed that the second harmonic is 32 dB below the fundamental frequency component. This circuit could offer an economic alternative to the conventional approaches, being an important contribution to increase the functionality of large area flexible electronics.