Abstract
The next evolution in cellular communications will not only improve upon the performance of previous generations, but also represent an unparalleled expansion in the number of services and use cases. One of the foundations for this evolution is the design of highly flexible, versatile, and resource-/power-efficient hardware components. This paper proposes and evaluates an FPGA-oriented baseband processing architecture suitable for communication scenarios such as non-contiguous carrier aggregation, centralized Cloud Radio Access Network (C-RAN) processing, and 4G/5G waveform coexistence. Our system is upgradeable, resource-efficient, cost-effective, and provides support for three 5G waveform candidates. Exploring Dynamic Partial Reconfiguration (DPR), the proposed architecture expands the design space exploration beyond the available hardware resources on the Zynq xc7z020 through hardware virtualization. Additionally, Dynamic Frequency Scaling (DFS) allows for run-time adjustment of processing throughput and reduces power consumption up to 88%. The resource overhead for DPR and DFS is residual, and the reconfiguration latency is two orders of magnitude below the control plane latency requirements proposed for 5G communications.

Abstract
The use of specialized accelerator circuits is a feasible solution to address performance and energy issues in embedded systems. This paper extends a previous field-programmable gate array-based approach that automatically generates pipelined customized loop accelerators (CLAs) from runtime instruction traces. Despite efficient acceleration, the approach suffered from high area and resource requirements when offloading a large number of kernels from the target application. This paper addresses this by enhancing the CLA with dynamic partial reconfiguration (DPR) support. Each kernel to accelerate is implemented as a variant of a reconfigurable area of the CLA which hosts all functional units and configuration memory. Evaluation of the proposed system is performed on a Virtex-7 device. We show, for a set of 21 kernels, that when comparing two CLAs capable of accelerating the same subset of kernels, the one which benefits from DPR can be up to 4.3x smaller. Resorting to DPR allows for the implementation of CLAs which support numerous kernels without a significant decrease in operating frequency and does not affect the initiation intervals at which kernels are scheduled. Finally, the area required by a CLA instance can be further reduced by increasing the IIs of the scheduled kernels.

Abstract
A new wearable data capture system for gait analysis is being developed. It consists of a pantyhose with embedded conductive yarns interconnecting customized sensing electronic devices that capture inertial and electromyographic signals and send aggregated information to a personal computer through a wireless link. The use of conductive yarns to build the myoelectric electrodes and the interconnections of the wired sensors network as well as the topology and functionality of the sensor modules are presented. © The Institution of Engineering and Technology 2017.

Abstract
This chapter presents a one-way method for synchronization at the media access control (MAC) layer of nodes and a circuit based on that in a wearable sensor network. The proposed approach minimizes the time skew with an accuracy of half of clock cycle in average. The work is intended to be used in a router integrated circuit (IC) designed for wearable systems. In particular, we address the need for good time synchronization in the simultaneous acquisition of surface electromyographic signals of several muscles. In our main application case, the electrodes are embedded in patient clothes connected to sensor nodes (SNs) equipped with analog-to-digital converters. The SNs are connected together in a network using conducting yarns embedded in the clothes. In the context of such wearable sensor networks, the main contributions of this work are the evaluation of existing protocols for synchronization, the description of a simpler, resource-efficient synchronization protocol, and its analysis, including the determination of the average local and global clock skew and of the synchronization probability in the presence of link failures. Both theoretical analysis and experimental results, in wired wearable networks, show that the proposed protocol has a better performance than precision time protocol (PTP), a standard timing protocol for both single and multihop situations. The proposed approach is simpler, requires no calculations, and exchanges fewer messages. Experimental results obtained with an implementation of the protocol in 0.35 µm complementary metal oxide semiconductor (CMOS) technology show that this approach keeps the one-hop average clock skew around 4.6 ns and peak-to-peak skew around 50 ns for a system clock frequency of 20 MHz. © The Institution of Engineering and Technology 2017.

Abstract
This chapter addresses a wearable body area network (BAN) system for both medical and nonmedical applications, especially those including a large number of sensors at BAN scale (<250), embedded in textile and with high data rate (<9+9 MHz) communication demands. The overall system includes an on-body central processing module (CPM) connected to a computer via a wireless link and a wearable sensor network. Due to the fixed location of the sensors and the possibility of using conductive yarns in textiles, a wired network has been considered for the wearable components. Employing conductive yarns instead of using wireless links provides a more reliable communication, higher data rates and throughput, and less power consumption. The wearable unit is composed of two types of circuits, the sensor nodes (SNs) and a base station (BS), all connected to each other with conductive yarns forming a mesh topology with the base node at the center. The reliability analysis shows that communication in a multi-hop connection of sensors in mesh topology is more reliable than in the conventional star topology. From the standpoint of the network, each SN is a four port router capable of handling packets from destination nodes to the BS. The end-to-end communication uses packet switching for packet delivery from SNs to the BS or in the reverse direction, or between SNs. The communication module has been implemented in a low power field programmable gate arrays (FPGA) and a microcontroller. The maximum data rate of the system is 9+9 Mbps while supporting tens of sensors, which is much more than current BAN applications need. The suitability of the proposed system for utilization in real applications has been demonstrated experimentally. © The Institution of Engineering and Technology 2017.

Abstract
Sequential Minimal Optimization (SMO) is the traditional training algorithm for Support Vector Machines (SVMs). However, SMO does not scale well with the size of the training set. For that reason, Stochastic Gradient Descent (SGD) algorithms, which have better scalability, are a better option for massive data mining applications. Furthermore, even with the use of SGD, training times can become extremely large depending on the data set. For this reason, accelerators such as Field-programmable Gate Arrays (FPGAs) are used. This work describes an implementation in hardware, using FPGA, of a fully parallel SVM using Stochastic Gradient Descent. The proposed FPGA implementation of an SVM with SGD presents speedups of more than 10,000x relative to software implementations running on a quad-core processor and up to 319x compared to state-of-the-art FPGA implementations while requiring fewer hardware resources. The results show that the proposed architecture is a viable solution for highly demanding problems such as those present in big data analysis.