Abstract

Abstract
The development of avionics systems is typically a tedious and cumbersome process. In addition to the required functions, developers must consider various and often conflicting non-functional requirements such as safety, performance, and energy efficiency. Certainly, an integrated approach with a seamless design flow that is capable of requirements modelling and supporting refinement down to an actual implementation in a traceable way, may lead to a significant acceleration of development cycles. This paper presents an aspect-oriented approach supported by a toolchain that deals with functional and non-functional requirements in an integrated manner. It also discusses how the approach can be applied to development of safety-critical systems and provides experimental results.

Abstract
The REFLECT project aimed at developing, validating, and evaluating a novel compilation and synthesis approach for heterogeneous multi-core computing systems that relies on aspect-oriented specifications to convey critical domain knowledge to all design/development stages of an integrated toolchain. To reach these goals, we have devised a new compilation and synthesis foundation combining distinct but synergistic areas of research, namely, aspect-oriented programming, hardware compilation, design patterns, and hardware templates. © Springer Science+Business Media New York 2013. All rights are reserved.

Abstract
A multi-mode circuit implements the functionality of a limited number of circuits, called modes, of which at any given time only one needs to be realised. Using run-time reconfiguration of an FPGA, all the modes can be implemented on the same reconfigurable region, requiring only an area that can contain the biggest mode. Typically, conventional run-time reconfiguration techniques generate a configuration for every mode separately. To switch between modes the complete reconfigurable region is rewritten, which often leads to very long reconfiguration times. In this paper we present a novel, fully automated tool flow that exploits similarities between the modes and uses Dynamic Circuit Specialization to drastically reduce reconfiguration time. Experimental results show that the number of bits that is rewritten in the configuration memory reduces with a factor from 4.6× to 5.1× without significant performance penalties. © 2013 EDAA.

Abstract
This chapter describes the CoSy1-based [1, 2] compilers developed in the context of the REFLECT project to support its aspect-oriented design-flow. In particular, these CoSy-based compilers are guided by LARA strategies and are responsible for generating code targeting traditional processors, as well as generating behavioral-RTL VHDL code [3] targeting hardware accelerators. Throughout this chapter, these compilers are referred collectively as reflectc, except when a specific compilation flow (with its specific name) is used. We also describe the compiler development extensions to support the REFLECT approach [4] and the weaving process controlled by LARA strategies [5-7] as described in Chap. 3. © Springer Science+Business Media New York 2013. All rights are reserved.

Abstract