Abstract
The high-performance requirements needed to implement the most advanced functionalities of current and future Cyber-Physical Systems (CPSs) are challenging the development processes of CPSs. On one side, CPSs rely on model-driven engineering (MDE) to satisfy the non-functional constraints and to ensure a smooth and safe integration of new features. On the other side, the use of complex parallel and heterogeneous embedded processor architectures becomes mandatory to cope with the performance requirements. In this regard, parallel programming models, such as OpenMP or CUDA, are a fundamental brick to fully exploit the performance capabilities of these architectures. However, parallel programming models are not compatible with current MDE approaches, creating a gap between the MDE used to develop CPSs and the parallel programming models supported by novel and future embedded platforms. The AMPERE project will bridge this gap by implementing a novel software architecture for the development of advanced CPSs. To do so, the proposed software architecture will be capable of capturing the definition of the components and communications described in the MDE framework, together with the non-functional properties, and transform it into key parallel constructs present in current parallel models, which may require extensions. These features will allow for making an efficient use of underlying parallel and heterogeneous architectures, while ensuring compliance with non-functional requirements, including those on real-time performance of the system.

Abstract
The growing trend to support parallel computation to enable the performance gains of the recent hardware architectures is increasingly present in more conservative domains, such as safety-critical systems. Applications such as autonomous driving require levels of performance only achievable by fully leveraging the potential parallelism in these architectures. To address this requirement, the Ada language, designed for safety and robustness, is considering to support parallel features in the next revision of the standard (Ada 202X). Recent works have motivated the use of OpenMP, a de facto standard in high-performance computing, to enable parallelism in Ada, showing the compatibility of the two models, and proposing static analysis to enhance reliability. This paper summarizes these previous efforts towards the integration of OpenMP into Ada to exploit its benefits in terms of portability, programmability and performance, while providing the safety benefits of Ada in terms of correctness. The paper extends those works proposing and evaluating an application transformation that enables the OpenMP and the Ada runtimes to operate (under certain restrictions) as they were integrated. The objective is to allow Ada programmers to (naturally) experiment and evaluate the benefits of parallelizing concurrent Ada tasks with OpenMP while ensuring the compliance with both specifications.

Abstract
The current proposal for the next revision of the Ada language considers the possibility to map the language parallel features to an underlying OpenMP runtime. As previously presented, and discussed in previous workshops, the works on fine-grain parallelism in Ada map well to the OpenMP tasking model for parallelism. Nevertheless, and although the general model of integration, and the semantic constructs are already reflected in the proposed revision of the standard, the integration of these new features with the Real-Time Systems Annex of Ada is still not complete. This paper presents an overview of what is supported and the still open issues.

Abstract
The new generation of smart systems require processing a vast amount of information from distributed data sources, while fulfilling non-functional properties related to real-time, energy-efficiency, communication quality and security. The ELASTIC software architecture is being developed to tackle this challenge, considering the complete continuum from the edge to the cloud. This paper provides a brief analysis of the smart application considered in the project, and the requirements emanating from their non-functional properties. The paper then identifies some of the technical constrains imposed to the ELASTIC software architecture to allow guaranteeing the non-functional requirements of the systems.

Abstract
Blood banks face inventory management problems associated to demand uncertainty and high inventory levels. An efficient blood inventory management is related to the use of simple, transparent and easy-to-understand procedures by blood banks’ employees. However, the literature about good practices in blood bank inventory management is scarce, reinforcing new developments need on this subject to ensure a good availability of blood products and reducing wastage. This research presents a blood inventory management system implemented in software, DOAR, able to meet demand while minimizing blood bags wastage. DOAR is simple, user-friendly and able to optimize blood inventory and donations. The purpose of the software is to provide a link between the demand by blood components and collected blood bags.

Abstract
The unprecedented pervasiveness of IoT systems is pushing this technology into increasingly stringent domains. Such application scenarios become even more challenging due to the demand for encompassing the interplay between safety and security. The IEEE 802.15.4 DSME MAC behavior aims at addressing such systems by providing additional deterministic, synchronous multi-channel access support. However, despite the several improvements over the previous versions of the protocol, the standard lacks a complete solution to secure communications. In this front, we propose the integration of TAKS, an hybrid cryptography scheme, over a standard DSME network. In this paper, we describe the system architecture for integrating TAKS into DSME with minimum impact to the standard, and we venture into analysing the overhead of having such security solution over application delay and throughput. After a performance analysis, we learn that it is possible to achieve a minor impact of 1% to 14% on top of the expected network delay, depending on the platform used, while still guaranteeing strong security support over the DSME network. © 2020 IEEE.