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About

I'm an Associate Professor at the Department of Computer Science, Faculty of Sciences, University of Porto and a researcher at the CRACS & INESC TEC research unit.

I received my PhD degree in Computer Science from the University of Porto in 2001 and my main research topics are the Design and Implementation of Logic Programming Systems, Tabling in Logic Programming and Parallel and Distributed Computing. Another areas of interest are Inductive Logic Programming, Probabilistic Logic Programming and Deductive Databases. I'm also one of the main developers of the Yap Prolog system with particular focus on the execution models that support tabling and parallel evaluation.

I've published more than 100 refereed papers in international journals, conferences and workshops, served more than 50 events as PC chair or PC member, served the ALP Board as executive committee member and the ALP Newsletter as area co-editor for the Implementations and Systems track, supervised several PhD/MSc students and had leading role in two national projects: projects STAMPA and LEAP. Currently, I also serve the INForum Board as president.

Interest
Topics
Details

Details

  • Name

    Ricardo Rocha
  • Cluster

    Computer Science
  • Role

    Assistant Centre Coordinator
  • Since

    01st January 2009
002
Publications

2021

On the correctness and efficiency of a novel lock-free hash trie map design

Authors
Areias, M; Rocha, R;

Publication
J. Parallel Distributed Comput.

Abstract
Hash tries are a trie-based data structure with nearly ideal characteristics for the implementation of hash maps. In this paper, we present a novel, simple and scalable hash trie map design that fully supports the concurrent search, insert and remove operations on hash maps. To the best of our knowledge, our proposal is the first that puts together the following characteristics: (i) be lock-free; (ii) use fixed size data structures; and (iii) maintain the access to all internal data structures as persistent memory references. Our design is modular enough to allow different types of configurations aimed for different performances in memory usage and execution time and can be easily implemented in any type of language, library or within other complex data structures. We discuss in detail the key algorithms required to easily reproduce our implementation by others and we present a proof of correctness showing that our proposal is linearizable and lock-free for the search, insert and remove operations. Experimental results show that our proposal is quite competitive when compared against other state-of-the-art proposals implemented in Java. © 2021 Elsevier Inc.

2021

On the Implementation of Memory Reclamation Methods in a Lock-Free Hash Trie Design

Authors
Moreno, P; Areias, M; Rocha, R;

Publication
Journal of Parallel and Distributed Computing

Abstract

2020

A compression-based design for higher throughput in a lock-free hash map

Authors
Moreno, P; Areias, M; Rocha, R;

Publication
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Abstract
Lock-free implementation techniques are known to improve the overall throughput of concurrent data structures. A hash map is an important data structure used to organize information that must be accessed frequently. A key role of a hash map is the ability to balance workloads by dynamically adjusting its internal data structures in order to provide the fastest possible access to the information. This work extends a previous lock-free hash map design to also support lock-free compression. The main goal is to significantly reduce the depth of the internal hash levels within the hash map, in order to minimize cache misses and increase the overall throughput. To materialize our design, we redesigned the existent search, insert, remove and expand operations in order to maintain the lock-freedom property of the whole design. Experimental results show that lock-free compression effectively improves the search operation and, in doing so, it outperforms the previous design, which was already quite competitive when compared against the concurrent hash map design supported by Intel. © Springer Nature Switzerland AG 2020.

2019

Multi-dimensional lock-free arrays for multithreaded mode-directed tabling in Prolog

Authors
Areias, M; Rocha, R;

Publication
Concurrency and Computation: Practice and Experience

Abstract

2019

A lock-free coalescing-capable mechanism for memory management

Authors
Leite, R; Rocha, R;

Publication
International Symposium on Memory Management, ISMM

Abstract
One common characteristic among current lock-free memory allocators is that they rely on the operating system to manage memory since they lack a lower-level mechanism capable of splitting and coalescing blocks of memory. In this paper, we discuss this problem and we propose a generic scheme for an efficient lock-free best-fit coalescing-capable mechanism that is able of satisfying memory allocation requests with desirable low fragmentation characteristics. © 2019 Association for Computing Machinery.

Supervised
thesis

2020

Lock-Free Memory Reclamation for Concurrent Hash Tries

Author
Paulo Jorge Teixeira Rosa

Institution
UP-FCUP

2020

Generic Lock-Free Memory Reclamation

Author
Pedro Carvalho Moreno

Institution
UP-FCUP

2019

Generic Lock-Free Memory Reclamation

Author
Pedro Carvalho Moreno

Institution
UP-FCUP

2018

Practical Lock-Free Dynamic Memory Allocation

Author
Ricardo Luís Pinheiro Leite

Institution
UP-FCUP

2018

Towards Efficient and Scalable Probabilistic Inductive Logic Programming

Author
Joana Sílvia Santos Côrte-Real

Institution
UP-FCUP