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About

About

I'm an Associate Professor at the Department of Computer Science, Faculty of Sciences, University of Porto and a researcher at the CRACS & INESC TEC research unit.

I received my PhD degree in Computer Science from the University of Porto in 2001 and my main research topics are the Design and Implementation of Logic Programming Systems, Tabling in Logic Programming and Parallel and Distributed Computing. Another areas of interest are Inductive Logic Programming, Probabilistic Logic Programming and Deductive Databases. I'm also one of the main developers of the Yap Prolog system with particular focus on the execution models that support tabling and parallel evaluation.

I've published more than 100 refereed papers in international journals, conferences and workshops, served more than 50 events as PC chair or PC member, served the ALP Board as executive committee member and the ALP Newsletter as area co-editor for the Implementations and Systems track, supervised several PhD/MSc students and had leading role in two national projects: projects STAMPA and LEAP. Currently, I also serve the INForum Board as president.

Interest
Topics
Details

Details

  • Name

    Ricardo Rocha
  • Cluster

    Computer Science
  • Role

    Centre Coordinator
  • Since

    01st January 2009
002
Publications

2022

On the correctness of a lock-free compression-based elastic mechanism for a hash trie design

Authors
Areias, M; Rocha, R;

Publication
COMPUTING

Abstract
A key aspect of any hash map design is the problem of dynamically resizing it in order to deal with hash collisions. Compression in tree-based hash maps is the ability of reducing the depth of the internal hash levels that support the hash map. In this context, elasticity refers to the ability of automatically resizing the internal data structures that support the hash map operations in order to meet varying workloads, thus optimizing the overall memory consumption of the hash map. This work extends a previous lock-free hash trie map design to support elastic hashing, i.e., expand saturated hash levels and compress unused hash levels, such that, at each point in time, the number of levels in a path is adjusted, as closely as possible, to the set of keys that is stored in the data structure. To materialize our design, we introduce a new compress operation for hash levels, which requires redesigning the existing search, insert, remove and expand operations in order to maintain the lock-freedom property of the data structure. Experimental results show that elasticity effectively improves the search operation and, in doing so, our design becomes very competitive when compared to other state-of-the-art designs implemented in Java.

2022

Parallel Logic Programming: A Sequel

Authors
Dovier, A; Formisano, A; Gupta, G; Hermenegildo, MV; Pontelli, E; Rocha, R;

Publication
THEORY AND PRACTICE OF LOGIC PROGRAMMING

Abstract

2021

On the correctness and efficiency of a novel lock-free hash trie map design

Authors
Areias, M; Rocha, R;

Publication
JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING

Abstract
Hash tries are a trie-based data structure with nearly ideal characteristics for the implementation of hash maps. In this paper, we present a novel, simple and scalable hash trie map design that fully supports the concurrent search, insert and remove operations on hash maps. To the best of our knowledge, our proposal is the first that puts together the following characteristics: (i) be lock-free; (ii) use fixed size data structures; and (iii) maintain the access to all internal data structures as persistent memory references. Our design is modular enough to allow different types of configurations aimed for different performances in memory usage and execution time and can be easily implemented in any type of language, library or within other complex data structures. We discuss in detail the key algorithms required to easily reproduce our implementation by others and we present a proof of correctness showing that our proposal is linearizable and lock-free for the search, insert and remove operations. Experimental results show that our proposal is quite competitive when compared against other state-of-the-art proposals implemented in Java. © 2021 Elsevier Inc.

2021

On the Implementation of Memory Reclamation Methods in a Lock-Free Hash Trie Design

Authors
Moreno, P; Areias, M; Rocha, R;

Publication
JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING

Abstract

2021

Towards an Elastic Lock-Free Hash Trie Design

Authors
Areias, M; Rocha, R;

Publication
2021 20TH INTERNATIONAL SYMPOSIUM ON PARALLEL AND DISTRIBUTED COMPUTING (ISPDC)

Abstract

Supervised
thesis

2022

Memory Reclamation for an Elastic Lockfree Hash Trie Map

Author
João Miguel Chamiça Pereira

Institution
UP-FCUP

2022

Generic Lock-Free Memory Reclamation

Author
Pedro Carvalho Moreno

Institution
UP-FCUP

2021

Elasticidade em Lock-Free Hash-Tries

Author
João Miguel Chamiça Pereira

Institution
UP-FCUP

2021

Generic Lock-Free Memory Reclamation

Author
Pedro Carvalho Moreno

Institution
UP-FCUP

2020

Generic Lock-Free Memory Reclamation

Author
Pedro Carvalho Moreno

Institution
UP-FCUP