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Details

  • Name

    Luís Miguel Sousa
  • Role

    Research Assistant
  • Since

    01st September 2022
  • Nationality

    Portugal
  • Contacts

    +351222094000
    luis.m.sousa@inesctec.pt
001
Publications

2024

A DSL and MLIR Dialect for Streaming and Vectorisation

Authors
da Silva, MC; Sousa, L; Paulino, N; Bispo, J;

Publication
APPLIED RECONFIGURABLE COMPUTING. ARCHITECTURES, TOOLS, AND APPLICATIONS, ARC 2024

Abstract
This work addresses the contemporary challenges in computing, caused by the stagnation of Moore's Law and Dennard scaling. The shift towards heterogeneous architectures necessitates innovative compilation strategies, prompting initiatives like the Multi-Level Intermediate Representation (MLIR) project, where progressive code lowering can be achieved through the use of dialects. Our work focuses on developing an MLIR dialect capable of representing streaming data accesses to memory, and Single Instruction Multiple Data (SIMD) vector operations. We also propose our own Structured Representation Language (SRL), a Design Specific Language (DSL) to serve as a precursor into the MLIR layer and subsequent inter-operation between new and existing dialects. The SRL exposes the streaming and vector computational concepts to a higher-level, and serves as intermediate step to supporting code generation containing our proposed dialect from arbitrary input code, which we leave as future work. This paper presents the syntaxes of the SRL DSL and of the dialect, and illustrates how we aim to employ them to target both General-Purpose Processors (GPPs) with SIMD co-processors and custom hardware options such as Field-Programmable Gate Arrayss (FPGAs) and Coarse-Grained Re-configurable Arrays (CGRAs).

Supervised
thesis

2023

Design, integration and experimental validation of a 2-bit Reconfigurable Intelligent Surface

Author
Ricardo Carvalho Araújo

Institution
UP-FEUP