Cookies Policy
The website need some cookies and similar means to function. If you permit us, we will use those means to collect data on your visits for aggregated statistics to improve our service. Find out More
Accept Reject
  • Menu
About

About

João M. P. Cardoso received his PhD degree in Electrical and Computer Engineering from the IST/UTL (Technical University of Lisbon), Lisbon, Portugal in 2001. He is currently Full Professor at the Department of Informatics Eng., Faculty of Eng. of the University of Porto, Porto, Portugal, and a research member of INESC TEC. Before, he was with the IST/UTL (2006-2008), a senior researcher at INESC-ID (2001-2009), and with the University of Algarve (1993-2006). In 2001/2002, he worked for PACT XPP Technologies, Inc., Munich, Germany. He has been involved in the organization and served as a Program Committee member for many international conferences. For example, he was general Co-Chair of IEEE/IFIP EUC’2015 and IEEE CSE’2015, General Chair of FPL’2013, General Co-Chair of ARC’2014 and ARC’2006, Program Co-Chair of ARCS’2016, DASIP’2014, and RAW’2010. He has (co-)authored over 150 scientific publications on subjects related to compilers, embedded systems, and reconfigurable computing. He has coordinated a number of research projects. He is a senior member of IEEE, a member of IEEE Computer Society, and a senior member of ACM.  His research interests include compilation techniques, domain-specific languages, reconfigurable computing, application-specific architectures, and high-performance computing with a particular emphasis in embedded computing.

Interest
Topics
Details

Details

  • Name

    João Paiva Cardoso
  • Role

    Senior Researcher
  • Since

    01st July 2011
002
Publications

2024

A Flexible-Granularity Task Graph Representation and Its Generation from C Applications (WIP)

Authors
Santos, T; Bispo, J; Cardoso, JMP;

Publication
PROCEEDINGS OF THE 25TH ACM SIGPLAN/SIGBED INTERNATIONAL CONFERENCE ON LANGUAGES, COMPILERS, AND TOOLS FOR EMBEDDED SYSTEMS, LCTES 2024

Abstract
Modern hardware accelerators, such as FPGAs, allow offloading large regions of C/C++ code in order to improve the execution time and/or the energy consumption of software applications. An outstanding challenge with this approach, however, is solving the Hardware/Software (Hw/Sw) partitioning problem. Given the increasing complexity of both the accelerators and the potential code regions, one needs to adopt a holistic approach when selecting an offloading region by exploring the interplay between communication costs, data usage patterns, and target-specific optimizations. To this end, we propose representing a C application as an extended task graph (ETG) with flexible granularity, which can be manipulated through the merging and splitting of tasks. This approach involves generating a task graph overlay on the program's Abstract Syntax Tree (AST) that maps tasks to functions and the flexible granularity operations onto inlining/outlining operations. This maintains the integrity and readability of the original source code, which is paramount for targeting different accelerators and enabling code optimizations, while allowing the offloading of code regions of arbitrary complexity based on the data patterns of their tasks. To evaluate the ETG representation and its compiler, we use the latter to generate ETGs for the programs in Rosetta and MachSuite benchmark suites, and extract several metrics regarding data communication, task-level parallelism, and dataflow patterns between pairs of tasks. These metrics provide important information that can be used by Hw/Sw partitioning methods.

2023

Electrical sensing of the plant Mimosa pudica under environmental temperatures

Authors
Lobo, MA; Cardoso, JMP; Rocha, PRF;

Publication
2023 IEEE 7TH PORTUGUESE MEETING ON BIOENGINEERING, ENBENG

Abstract
Plants gather and process information about their surroundings to make decisions that prioritize their well-being while considering the environment. These decisions are conveyed through electrical signals within and between cells, mainly in the form of action and variation potentials, in response to stimuli, including mechanical vibrations, changes in temperature, light intensity, and humidity. Although the ability of some plants, such as the Mimosa pudica, to react to sudden environmental stimuli (e.g., touch) is well known, their long-term electrical response under slow environmental changes remains not fully understood. Here, a multi-source monitoring system has been developed to collect and store electrical signals from the plant Mimosa pudica, and surrounding environmental temperature and humidity, over a period of approximately 5 days. A realtime dashboard shows the environmental temperature and variation potential (VP) from Mimosa pudica. The VP mimics the environmental temperature changes, with an associated delay. Our long-term physiological observations suggest that environmental temperature sensing in the plant Mimosa pudica can be monitored and is likely driven by bioelectricity.

2023

A Study on Hyperparameters Configurations for an Efficient Human Activity Recognition System

Authors
Ferreira, PJS; Mendes-Moreira, J; Cardoso, JMP;

Publication
PROCEEDINGS OF THE 8TH INTERNATIONAL WORKSHOP ON SENSOR-BASED ACTIVITY RECOGNITION AND ARTIFICIAL INTELLIGENCE, IWOAR 2023

Abstract
Human Activity Recognition (HAR) has been a popular research field due to the widespread of devices with sensors and computational power (e.g., smartphones and smartwatches). Applications for HAR systems have been extensively researched in recent literature, mainly due to the benefits of improving quality of life in areas like health and fitness monitoring. However, since persons have different motion patterns when performing physical activities, a HAR system would need to adapt to the characteristics of the user in order to maintain or improve accuracy. Mobile devices, such as smartphones, used to implement HAR systems, have limited resources (e.g., battery life). They also have difficulty adapting to the device's constraints to work efficiently for long periods. In this work, we present a kNN-based HAR system and an extensive study of the influence of hyperparameters (window size, overlap, distance function, and the value of k) and parameters (sampling frequency) on the system accuracy, energy consumption, and response time. We also study how hyperparameter configurations affect the model's performance for the users and the activities. Experimental results show that adapting the hyperparameters makes it possible to adjust the system's behavior to the user, the device, and the target service. These results motivate the development of a HAR system capable of automatically adapting the hyperparameters for the user, the device, and the service.

2023

A DSL-based runtime adaptivity framework for Java

Authors
Carvalho, T; Bispo, J; Pinto, P; Cardoso, JMP;

Publication
SOFTWAREX

Abstract
This article presents Kadabra, a Java source-to-source compiler that allows users to make code queries, code analysis and code transformations, all user-programmable using the domain-specific language LARA. We show how Kadabra can be used as the basis for developing a runtime autotuning and adaptivity framework, able to adapt existing source Java code in order to take advantage of runtime autotuning. Specifically, this article presents the framework, consisting of Kadabra and an API for runtime adaptivity. We show the use of the framework to extend Java applications with autotuning and runtime adaptivity mechanisms to target performance improvement and/or energy saving goals.(c) 2023 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/).

2023

Preface ASAP 2023

Authors
Cardoso, JMP; Jimborean, A; Mentens, N; Coutinho, JGF;

Publication
34th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2023, Porto, Portugal, July 19-21, 2023

Abstract
[No abstract available]

Supervised
thesis

2023

Energy-Computing Efficient Classification Techniques for Mobile-Based HAR Systems

Author
Paulo Jorge Silva Ferreira

Institution
UP-FEUP

2023

Source-to-source Programmable Performance Engineering For High-Performance Computing

Author
Pedro Miguel dos Santos Pinto

Institution
UP-FEUP

2023

A Holistic Approach for Partitioning and Optimizing Software Applications on FPGAs

Author
Tiago Lascasas dos Santos

Institution
UP-FEUP

2023

FPGA-based kNN Accelerators via High-Level Synthesis

Author
André Filipe Ferreira da Silva

Institution
UP-FEUP

2023

Plants as Sensors: First Studies and Prototype Models

Author
Maria Marta Nunes Andrade Lobo dos Santos

Institution
UP-FEUP