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Sobre

Sobre

João M. P. Cardoso obteve o grau de Doutor em Engenharia Electrotécnica e Computadores no IST/UTL (Instituto Superior Técnico/Universidade Técnica de Lisboa), Lisboa, Portugal, em 2001. É actualmente Professor Catedrático no Departamento de Engenharia Informática (DEI) da Faculdade de Engenharia da Universidade do Porto (FEUP) e investigador sénior no INESC TEC. Previamente, ele foi Prof. Auxiliar no IST/UTL (2006-2008), investigador sénior no INESC-ID (2001-2009), e Prof. Auxiliar na Universidade do Algarve (1993-2006). Em 2001/2002, trabalhou na PACT XPP Technologies, Inc., em Munique, Alemanha. Tem estado envolvido na organização e tem servido como membro do comité científico de muitas conferências internacionais. Por exemplo, foi General Co-Chair da IEEE/IFIP EUC’2015 e da IEEE CSE’2015, General Chair da FPL’2013, General Co-Chair da ARC’2014 e ARC’2006, Program Co-Chair da ARCS’2016, DASIP’2014, e RAW’2010. É co-autor de mais de 150 publicações científicas em tópicos relacionados com compiladores, sistemas embebidos, e computação reconfigurável. Coordenou vários projectos de investigação. É um membro sénior do IEEE e do ACM e membro da IEEE Computer Society. Os seus interesses de investigação incluem técnicas de compiladores, linguages específicas ao domínio, computação reconfigurável, arquitecturas específicas à aplicação, e computação de elevado desempenho com ênfase em computação embebida.

Tópicos
de interesse
Detalhes

Detalhes

  • Nome

    João Paiva Cardoso
  • Cluster

    Informática
  • Cargo

    Investigador Sénior
  • Desde

    01 julho 2011
002
Publicações

2019

Dynamic Partial Reconfiguration of Customized Single-Row Accelerators

Autores
Paulino, NMC; Ferreira, JC; Cardoso, JMP;

Publicação
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Abstract

2019

Supporting the Scale-up of High Performance Application to Pre-Exascale Systems: The ANTAREX Approach

Autores
Silvano, C; Agosta, G; Bartolini, A; Beccari, AR; Benini, L; Besnard, L; Bispo, J; Cmar, R; Cardoso, JMP; Cavazzoni, C; Cesarini, D; Cherubin, S; Ficarelli, F; Gadioli, D; Golasowski, M; Lasri, I; Libri, A; Manelfi, C; Martinovic, J; Palermo, G; Pinto, P; Rohou, E; Sanna, N; Slaninova, K; Vitali, E;

Publicação
2019 27TH EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED AND NETWORK-BASED PROCESSING (PDP)

Abstract
The ANTAREX project developed an approach to the performance tuning of High Performance applications based on an Aspect-oriented Domain Specific Language (DSL), with the goal to simplify the enforcement of extra-functional properties in large scale applications. The project aims at demonstrating its tools and techniques on two relevant use cases, one in the domain of computational drug discovery, the other in the domain of online vehicle navigation. In this paper, we present an overview of the project and of its main achievements, as well as of the large scale experiments that have been planned to validate the approach.

2019

Graph-Based Code Restructuring Targeting HLS for FPGAs

Autores
Ferreira, AC; Cardoso, JMP;

Publicação
Applied Reconfigurable Computing - 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9-11, 2019, Proceedings

Abstract
High-level synthesis (HLS) is of paramount importance to enable software developers to map critical computations to FPGA-based hardware accelerators. However, in order to generate efficient hardware accelerators one needs to apply significant code transformations and adequately use the directive-driven approach, part of most HLS tools. The code restructuring and directives needed are dependent not only of the characteristics of the input code but also of the HLS tools and target FPGAs. These aspects require a deep knowledge about the subjects involved and tend to exclude software developers. This paper presents our recent approach for automatic code restructuring targeting HLS tools. Our approach uses an unfolded graph representation, which can be generated from program execution traces, and graph-based optimizations, such as folding, to generate suitable HLS C code. In this paper, we describe the approach and the new optimizations proposed. We evaluate the approach with a number of representative kernels and the results show its capability to generating efficient hardware implementations only achievable using manual restructuring of the input software code and manual insertion of adequate HLS directives. © 2019, Springer Nature Switzerland AG.

2019

The ANTAREX domain specific language for high performance computing

Autores
Silvano, C; Agosta, G; Bartolini, A; Beccari, AR; Benini, L; Besnard, L; Bispo, J; Cmar, R; Cardoso, JMP; Cavazzoni, C; Cesarini, D; Cherubin, S; Ficarelli, F; Gadioli, D; Golasowski, M; Libri, A; Martinovic, J; Palermo, G; Pinto, P; Rohou, E; Slaninova, K; Vitali, E;

Publicação
MICROPROCESSORS AND MICROSYSTEMS

Abstract
The ANTAREX project relies on a Domain Specific Language (DSL) based on Aspect Oriented Programming (AOP) concepts to allow applications to enforce extra functional properties such as energy-efficiency and performance and to optimize Quality of Service (QoS) in an adaptive way. The DSL approach allows the definition of energy-efficiency, performance, and adaptivity strategies as well as their enforcement at runtime through application autotuning and resource and power management. In this paper, we present an overview of the key outcome of the project, the ANTAREX DSL, and some of its capabilities through a number of examples, including how the DSL is applied in the context of the project use cases.

2019

Message from the symposium general chair and program chairs

Autores
Shibata, Y; Cardoso, JMP; Takamaeda Yamazaki, S;

Publicação
ACM International Conference Proceeding Series

Abstract

Teses
supervisionadas

2016

0

Autor
Rosária Maria Afonso Rodrigues de Melo

Instituição
UP-FCNA

2016

Multitarget Compilation Techniques for Generating E_cient OpenCL Code from Matrix-oriented Computations

Autor
Luis Alexandre Cubal dos Reis

Instituição
UP-FEUP

2016

Runtime-aware Compiler Optimizations for High-Performance Embedded Computing

Autor
Pedro Miguel dos Santos Pinto

Instituição
UP-FEUP

2016

RAVEN: a Node.js Static Metadata Extracting Solution for JavaScript Applications

Autor
Carlos Maria Antunes Matias

Instituição
UP-FEUP

2016

Exploiting JavaScript Birthmarking Techniques for Code Theft Detection

Autor
João Carlos Costa Pinto

Instituição
UP-FEUP