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Sobre

Sobre

João M. P. Cardoso obteve o grau de Doutor em Engenharia Electrotécnica e Computadores no IST/UTL (Instituto Superior Técnico/Universidade Técnica de Lisboa), Lisboa, Portugal, em 2001. É actualmente Professor Catedrático no Departamento de Engenharia Informática (DEI) da Faculdade de Engenharia da Universidade do Porto (FEUP) e investigador sénior no INESC TEC. Previamente, ele foi Prof. Auxiliar no IST/UTL (2006-2008), investigador sénior no INESC-ID (2001-2009), e Prof. Auxiliar na Universidade do Algarve (1993-2006). Em 2001/2002, trabalhou na PACT XPP Technologies, Inc., em Munique, Alemanha. Tem estado envolvido na organização e tem servido como membro do comité científico de muitas conferências internacionais. Por exemplo, foi General Co-Chair da IEEE/IFIP EUC’2015 e da IEEE CSE’2015, General Chair da FPL’2013, General Co-Chair da ARC’2014 e ARC’2006, Program Co-Chair da ARCS’2016, DASIP’2014, e RAW’2010. É co-autor de mais de 150 publicações científicas em tópicos relacionados com compiladores, sistemas embebidos, e computação reconfigurável. Coordenou vários projectos de investigação. É um membro sénior do IEEE e do ACM e membro da IEEE Computer Society. Os seus interesses de investigação incluem técnicas de compiladores, linguages específicas ao domínio, computação reconfigurável, arquitecturas específicas à aplicação, e computação de elevado desempenho com ênfase em computação embebida.

Tópicos
de interesse
Detalhes

Detalhes

  • Nome

    João Paiva Cardoso
  • Cargo

    Investigador Sénior
  • Desde

    01 julho 2011
002
Publicações

2025

First Twenty Years of the International Symposium on Applied Reconfigurable Computing (ARC): A Selection of Papers

Autores
Cardoso, JMP; Najjar, WA;

Publicação
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 21st International Symposium, ARC 2025, Seville, Spain, April 9-11, 2025, Proceedings

Abstract
The International Symposium on Applied Reconfigurable Computing (ARC) is an annual forum for the discussion and dissemination of research, notably applying the Reconfigurable Computing (RC) concept to real-world problems. The first edition of ARC took place in 2005, and in 2024, ARC celebrated its 20th edition. During those 20 years, the field of reconfigurable computing saw a tremendous growth in its underlying technology. ARC contributed very significantly to the presentation and dissemination of new ideas, innovative applications, and fruitful discussions, all of which have resulted in the shaping of novel lines of research. Here, we present selected papers from the first 20 years of ARC, that we believe represent the corpus of work and reflect the ARC spirit by covering a broad spectrum of RC applications, benchmarks, tools, and architectures. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

2024

A Flexible-Granularity Task Graph Representation and Its Generation from C Applications (WIP)

Autores
Santos, T; Bispo, J; Cardoso, JMP;

Publicação
PROCEEDINGS OF THE 25TH ACM SIGPLAN/SIGBED INTERNATIONAL CONFERENCE ON LANGUAGES, COMPILERS, AND TOOLS FOR EMBEDDED SYSTEMS, LCTES 2024

Abstract
Modern hardware accelerators, such as FPGAs, allow offloading large regions of C/C++ code in order to improve the execution time and/or the energy consumption of software applications. An outstanding challenge with this approach, however, is solving the Hardware/Software (Hw/Sw) partitioning problem. Given the increasing complexity of both the accelerators and the potential code regions, one needs to adopt a holistic approach when selecting an offloading region by exploring the interplay between communication costs, data usage patterns, and target-specific optimizations. To this end, we propose representing a C application as an extended task graph (ETG) with flexible granularity, which can be manipulated through the merging and splitting of tasks. This approach involves generating a task graph overlay on the program's Abstract Syntax Tree (AST) that maps tasks to functions and the flexible granularity operations onto inlining/outlining operations. This maintains the integrity and readability of the original source code, which is paramount for targeting different accelerators and enabling code optimizations, while allowing the offloading of code regions of arbitrary complexity based on the data patterns of their tasks. To evaluate the ETG representation and its compiler, we use the latter to generate ETGs for the programs in Rosetta and MachSuite benchmark suites, and extract several metrics regarding data communication, task-level parallelism, and dataflow patterns between pairs of tasks. These metrics provide important information that can be used by Hw/Sw partitioning methods.

2024

Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2024, Porto, Portugal, June 19-21, 2024

Autores
Josipovic, L; Zhou, P; Shanker, S; Cardoso, JMP; Anderson, J; Yuichiro, S;

Publicação
HEART

Abstract

2024

A Fast and Energy-Efficient Method for Online and Incremental Pareto-Front Update

Autores
Ferreira, PJS; Moreira, JM; Cardoso, JMP;

Publicação
10th IEEE World Forum on Internet of Things, WF-IoT 2024, Ottawa, ON, Canada, November 10-13, 2024

Abstract
Self-adaptive Systems (SaS) are becoming increasingly important for adapting to dynamic environments and for optimizing performance on resource-constrained devices. A practical approach to achieving self-adaptability involves using a Pareto-Front (PF) to store the system's hyper-parameters and the outcomes of hyperparameter combinations. This paper proposes a novel method to approximate a PF, offering a configurable number of solutions that can be adapted to the device's limitations. We conducted extensive experiments across various scenarios, where all PF solutions were replaced, and real world scenarios were performed using actual measurements from a Human Activity Recognition (HAR) system. Our results show that our method consistently outperforms previous methods, mainly when the maximum number of PF solutions is in the order of hundreds. The effectiveness of our method is most apparent in real-case scenarios where it achieves, when executed in a Raspberry Pi 5, up to 87% energy consumption reduction and lower execution times than the second-best algorithm. Additionally, our method ensures a more evenly distributed solution across the PF, preventing the high concentration of solutions. © 2024 IEEE.

2023

Electrical sensing of the plant Mimosa pudica under environmental temperatures

Autores
Lobo, MA; Cardoso, JMP; Rocha, PRF;

Publicação
2023 IEEE 7TH PORTUGUESE MEETING ON BIOENGINEERING, ENBENG

Abstract
Plants gather and process information about their surroundings to make decisions that prioritize their well-being while considering the environment. These decisions are conveyed through electrical signals within and between cells, mainly in the form of action and variation potentials, in response to stimuli, including mechanical vibrations, changes in temperature, light intensity, and humidity. Although the ability of some plants, such as the Mimosa pudica, to react to sudden environmental stimuli (e.g., touch) is well known, their long-term electrical response under slow environmental changes remains not fully understood. Here, a multi-source monitoring system has been developed to collect and store electrical signals from the plant Mimosa pudica, and surrounding environmental temperature and humidity, over a period of approximately 5 days. A realtime dashboard shows the environmental temperature and variation potential (VP) from Mimosa pudica. The VP mimics the environmental temperature changes, with an associated delay. Our long-term physiological observations suggest that environmental temperature sensing in the plant Mimosa pudica can be monitored and is likely driven by bioelectricity.

Teses
supervisionadas

2023

Code Specialization for Targeting FPGAs via High-Level Synthesis Tools

Autor
Vitória Alexa Maciel Correia

Instituição
UP-FEUP

2023

Energy-Computing Efficient Classification Techniques for Mobile-Based HAR Systems

Autor
Paulo Jorge Silva Ferreira

Instituição
UP-FEUP

2023

Source-to-source Programmable Performance Engineering For High-Performance Computing

Autor
Pedro Miguel dos Santos Pinto

Instituição
UP-FEUP

2023

A Holistic Approach for Partitioning and Optimizing Software Applications on FPGAs

Autor
Tiago Lascasas dos Santos

Instituição
UP-FEUP

2023

FPGA-based kNN Accelerators via High-Level Synthesis

Autor
André Filipe Ferreira da Silva

Instituição
UP-FEUP