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João M. P. Cardoso obteve o grau de Doutor em Engenharia Electrotécnica e Computadores no IST/UTL (Instituto Superior Técnico/Universidade Técnica de Lisboa), Lisboa, Portugal, em 2001. É actualmente Professor Catedrático no Departamento de Engenharia Informática (DEI) da Faculdade de Engenharia da Universidade do Porto (FEUP) e investigador sénior no INESC TEC. Previamente, ele foi Prof. Auxiliar no IST/UTL (2006-2008), investigador sénior no INESC-ID (2001-2009), e Prof. Auxiliar na Universidade do Algarve (1993-2006). Em 2001/2002, trabalhou na PACT XPP Technologies, Inc., em Munique, Alemanha. Tem estado envolvido na organização e tem servido como membro do comité científico de muitas conferências internacionais. Por exemplo, foi General Co-Chair da IEEE/IFIP EUC’2015 e da IEEE CSE’2015, General Chair da FPL’2013, General Co-Chair da ARC’2014 e ARC’2006, Program Co-Chair da ARCS’2016, DASIP’2014, e RAW’2010. É co-autor de mais de 150 publicações científicas em tópicos relacionados com compiladores, sistemas embebidos, e computação reconfigurável. Coordenou vários projectos de investigação. É um membro sénior do IEEE e do ACM e membro da IEEE Computer Society. Os seus interesses de investigação incluem técnicas de compiladores, linguages específicas ao domínio, computação reconfigurável, arquitecturas específicas à aplicação, e computação de elevado desempenho com ênfase em computação embebida.

Tópicos
de interesse
Detalhes

Detalhes

  • Nome

    João Paiva Cardoso
  • Cluster

    Informática
  • Cargo

    Investigador Sénior
  • Desde

    01 julho 2011
003
Publicações

2020

A Study on Hyperparameter Configuration for Human Activity Recognition

Autores
Crarcia, KD; Carvalho, T; Mendes Moreira, J; Cardoso, JMP; de Carvalho, ACPLF;

Publicação
14th International Conference on Soft Computing Models in Industrial and Environmental Applications (SOCO 2019) - Seville, Spain, May 13-15, 2019, Proceedings

Abstract
Human Activity Recognition is a machine learning task for the classification of human physical activities. Applications for that task have been extensively researched in recent literature, specially due to the benefits of improving quality of life. Since wearable technologies and smartphones have become more ubiquitous, a large amount of information about a person’s life has become available. However, since each person has a unique way of performing physical activities, a Human Activity Recognition system needs to be adapted to the characteristics of a person in order to maintain or improve accuracy. Additionally, when smartphones devices are used to collect data, it is necessary to manage its limited resources, so the system can efficiently work for long periods of time. In this paper, we present a semi-supervised ensemble algorithm and an extensive study of the influence of hyperparameter configuration in classification accuracy. We also investigate how the classification accuracy is affected by the person and the activities performed. Experimental results show that it is possible to maintain classification accuracy by adjusting hyperparameters, like window size and window overlap, depending on the person and activity performed. These results motivate the development of a system able to automatically adapt hyperparameter settings for the activity performed by each person. © 2020, Springer Nature Switzerland AG.

2020

Improving performance and energy consumption in embedded systems via binary acceleration: A survey

Autores
Paulino, N; Ferreira, JC; Cardoso, JMP;

Publicação
ACM Computing Surveys

Abstract
The breakdown of Dennard scaling has resulted in a decade-long stall of the maximum operating clock frequencies of processors. To mitigate this issue, computing shifted to multi-core devices. This introduced the need for programming flows and tools that facilitate the expression of workload parallelism at high abstraction levels. However, not all workloads are easily parallelizable, and the minor improvements to processor cores have not significantly increased single-threaded performance. Simultaneously, Instruction Level Parallelism in applications is considerably underexplored. This article reviews notable approaches that focus on exploiting this potential parallelism via automatic generation of specialized hardware from binary code. Although research on this topic spans over more than 20 years, automatic acceleration of software via translation to hardware has gained new importance with the recent trend toward reconfigurable heterogeneous platforms. We characterize this kind of binary acceleration approach and the accelerator architectures on which it relies. We summarize notable state-of-the-art approaches individually and present a taxonomy and comparison. Performance gains from 2.6× to 5.6× are reported, mostly considering bare-metal embedded applications, along with power consumption reductions between 1.3× and 3.9×. We believe the methodologies and results achievable by automatic hardware generation approaches are promising in the context of emergent reconfigurable devices. © 2020 Association for Computing Machinery.

2020

Compilation of MATLAB computations to CPU/GPU via C/OpenCL generation

Autores
Reis, L; Bispo, J; Cardoso, JMP;

Publicação
Concurrency Computation

Abstract
In order to take advantage of the processing power of current computing platforms, programmers typically need to develop software versions for different target devices. This task is time-consuming and requires significant programming and computer architecture expertise. A possible and more convenient alternative is to start with a single high-level description of a program with minimum implementation details, and generate custom implementations according to the target platform. In this paper, we use MATLAB as a high-level programming language and propose a compiler that targets CPU/GPU computing platforms by generating customized implementations in C and OpenCL. We propose a number of compiler techniques to automatically generate efficient C and OpenCL code from MATLAB programs. One of such compiler techniques relies on heuristics to decide when and how to use Shared Virtual Memory (SVM). The experimental results show that our approach is able to generate code that provides significant speedups (eg, geometric mean speedup of 11× for a set of simple benchmarks) using a discrete GPU over equivalent sequential C code executing on a CPU. With more complex benchmarks, for which only some code regions can be parallelized, and are thus offloaded, the generated code achieved speedups of up to 2.2×. We also show the impact of using SVM, specifically fine-grained buffers, and the results show that the compiler is able to achieve significant speedups, both over the versions without SVM and with naïve aggressive SVM use, across three CPU/GPU platforms. © 2020 John Wiley & Sons, Ltd.

2019

Dynamic Partial Reconfiguration of Customized Single-Row Accelerators

Autores
Paulino, NMC; Ferreira, JC; Cardoso, JMP;

Publicação
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Abstract

2019

Fast Heuristic-Based GPU Compiler Sequence Specialization

Autores
Nobre, R; Reis, L; Cardoso, JMP;

Publicação
Euro-Par 2018: Parallel Processing Workshops - Euro-Par 2018 International Workshops, Turin, Italy, August 27-28, 2018, Revised Selected Papers

Abstract

Teses
supervisionadas

2019

Energy Efficient Smartphone-based Users Activity Classification

Autor
Ricardo Manuel Correia Magalhães

Instituição
UP-FEUP

2019

Runtime-aware Compiler Optimizations for High-Performance Embedded Computing

Autor
Pedro Miguel dos Santos Pinto

Instituição
UP-FEUP

2019

From Binary to Multi-Class Divisions: improvements on Hierarchical Divisive Human Activity Recognition

Autor
Tomás Vieira Caldas

Instituição
UP-FEUP

2019

Programming and mapping strategies for embedded computing runtime adaptability

Autor
Tiago Diogo Ribeiro de Carvalho

Instituição
UP-FEUP

2019

Acceleration of Applications with FPGA-Based Computing Machines: New DSL

Autor
Daniel Alexandre Pimenta Lopes Fernandes

Instituição
UP-FEUP