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About

About

I received the Ph.D. degree in Electrical and  Computer Engineering from the University of Porto (Portugal) in 2001. I 'm currently an assistant professor with the Faculty of Engineering, University of Porto, and a senior researcher at INESC TEC. I'm a member of IEEE, ACM and Euromicro.


My research interests center around the design of dedicated digital systems for complex and demanding embedded applications. I'm particularly interested in three areas:

  • Design of self-adaptive digital systems
  • FPGA-based reconfigurable computing
  • Hardware acceleration of embedded systems
  • Some concrete research topics are:

    • dynamic reconfiguration of FPGAs
    • generation of FPGA configurations at run-time
    • fast physical synthesis for digital circuits
    • virtual programmable hardware architectures
    • transparent task migration from software→hardware

    Interest
    Topics
    Details

    Details

    004
    Publications

    2019

    An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios

    Authors
    Ferreira, ML; Ferreira, JC;

    Publication
    ELECTRONICS

    Abstract
    The next evolution in cellular communications will not only improve upon the performance of previous generations, but also represent an unparalleled expansion in the number of services and use cases. One of the foundations for this evolution is the design of highly flexible, versatile, and resource-/power-efficient hardware components. This paper proposes and evaluates an FPGA-oriented baseband processing architecture suitable for communication scenarios such as non-contiguous carrier aggregation, centralized Cloud Radio Access Network (C-RAN) processing, and 4G/5G waveform coexistence. Our system is upgradeable, resource-efficient, cost-effective, and provides support for three 5G waveform candidates. Exploring Dynamic Partial Reconfiguration (DPR), the proposed architecture expands the design space exploration beyond the available hardware resources on the Zynq xc7z020 through hardware virtualization. Additionally, Dynamic Frequency Scaling (DFS) allows for run-time adjustment of processing throughput and reduces power consumption up to 88%. The resource overhead for DPR and DFS is residual, and the reconfiguration latency is two orders of magnitude below the control plane latency requirements proposed for 5G communications.

    2019

    Dynamic Partial Reconfiguration of Customized Single-Row Accelerators

    Authors
    Cardanha Paulino, NM; Ferreira, JC; Cardoso, JMP;

    Publication
    IEEE Trans. VLSI Syst.

    Abstract

    2019

    Dynamic Partial Reconfiguration of Customized Single-Row Accelerators

    Authors
    Paulino, NMC; Ferreira, JC; Cardoso, JMP;

    Publication
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

    Abstract

    2018

    An FPGA array for cellular genetic algorithms: Application to the minimum energy broadcast problem

    Authors
    dos Santos, PV; Alves, JC; Ferreira, JC;

    Publication
    Microprocessors and Microsystems

    Abstract
    The genetic algorithm is a general purpose optimization metaheuristic for solving complex optimization problems. Because the algorithm usually requires a large number of iterations to evolve a population of solutions to good final solutions, it normally exhibits long execution times, especially if running on low-performance conventional processors. In this work, we present a scalable computing array to parallelize and accelerate the execution of cellular GAs (cGAs). This is a variant of genetic algorithms which can conveniently exploit the coarse-grain parallelism afforded by custom parallel processing. The proposed architecture targets Xilinx FPGAs and was implemented as an auxiliary processor of an embedded soft-core CPU (MicroBlaze). To facilitate the customization for different optimization problems, a high-level synthesis design flow is proposed where the problem-dependent operations are specified in C++ and synthesised to custom hardware, thus demanding of the programmer only minimal knowledge of low-level digital design for FPGAs. To demonstrate the efficiency of the array processor architecture and the effectiveness of the design methodology, the development of a hardware solver for the minimum energy broadcast problem in wireless ad hoc networks is employed as a use case. Implementation results for a Virtex-6 FPGA show significant speedups, especially when comparing to embedded processors used in current FPGA devices. © 2018

    2018

    A parallel-pipelined OFDM baseband modulator with dynamic frequency scaling for 5G systems

    Authors
    Ferreira, ML; Ferreira, JC; Hübner, M;

    Publication
    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

    Abstract
    5G heterogeneity will cover a huge diversity of use cases, ranging from enhanced-broadband to low-throughput and low-power communications. To address such requirements variety, this paper proposes a parallel-pipelined architecture for an OFDM baseband modulator with clock frequency run-time adaptation through dynamic frequency scaling (DFS). It supports a set of OFDM numerologies recently proposed for 5G communication systems. The parallel-pipelined architecture can achieve high throughputs at low clock frequencies (up to 520.3 MSamples/s at 160 MHz) and DFS allows for the adjustment of baseband processing clock frequency according to immediate throughput demands. The application of DFS increases the system’s power efficiency by allowing power savings up to 62.5%; the resource and latency overhead is negligible. © Springer International Publishing AG, part of Springer Nature 2018.

    Supervised
    thesis

    2017

    VLSI design of configurable low-power coarse-grained array architecture

    Author
    Diogo Alexandre Ribeiro de Sousa

    Institution
    UP-FEUP

    2017

    Automatic implementation of a re-configurable logic over ASIC design flow

    Author
    José Delfim Ribeiro Valverde

    Institution
    UP-FEUP

    2017

    Configurable coarse-grained array architecture for processing of biological signals

    Author
    João Pedro Sauvarin Lopes

    Institution
    UP-FEUP

    2017

    FPGA implementation of a baseband processor for FBMC transmission

    Author
    Miguel Nuno Marques Vaz de Carvalho

    Institution
    UP-FEUP

    2017

    "Profiling" por hardware em tempo real para sistemas embebidos

    Author
    Rui Miguel Almeida Alves

    Institution
    UP-FEUP