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About

I received the Ph.D. degree in Electrical and  Computer Engineering from the University of Porto (Portugal) in 2001. I 'm currently an assistant professor with the Faculty of Engineering, University of Porto, and a senior researcher at INESC TEC. I'm a member of IEEE, ACM and Euromicro.


My research interests center around the design of dedicated digital systems for complex and demanding embedded applications. I'm particularly interested in three areas:

  • Design of self-adaptive digital systems
  • FPGA-based reconfigurable computing
  • Hardware acceleration of embedded systems
  • Some concrete research topics are:

    • dynamic reconfiguration of FPGAs
    • generation of FPGA configurations at run-time
    • fast physical synthesis for digital circuits
    • virtual programmable hardware architectures
    • transparent task migration from software→hardware

    Interest
    Topics
    Details

    Details

    005
    Publications

    2021

    Transparent Control Flow Transfer between CPU and Accelerators for HPC

    Authors
    Granhao, D; Ferreira, JC;

    Publication
    Electronics

    Abstract
    Heterogeneous platforms with FPGAs have started to be employed in the High-Performance Computing (HPC) field to improve performance and overall efficiency. These platforms allow the use of specialized hardware to accelerate software applications, but require the software to be adapted in what can be a prolonged and complex process. The main goal of this work is to describe and evaluate mechanisms that can transparently transfer the control flow between CPU and FPGA within the scope of HPC. Combining such a mechanism with transparent software profiling and accelerator configuration could lead to an automatic way of accelerating regular applications. In this work, a mechanism based on the ptrace system call is proposed, and its performance on the Intel Xeon+FPGA platform is evaluated. The feasibility of the proposed approach is demonstrated by a working prototype that performs the transparent control flow transfer of any function call to a matching hardware accelerator. This approach is more general than shared library interposition at the cost of a small time overhead in each accelerator use (about 1.3ms in the prototype implementation).

    2021

    A Binary Translation Framework for Automated Hardware Generation

    Authors
    Paulino, N; Bispo, J; Ferreira, JC; Cardoso, JMP;

    Publication
    IEEE Micro

    Abstract

    2021

    Pedagogical Innovation in Pandemic Times: The Experience of a Microprocessor Programming Course

    Authors
    Lima, B; Granhão, D; Araújo, AJ; Ferreira, JC;

    Publication
    2021 4th International Conference of the Portuguese Society for Engineering Education (CISPEE)

    Abstract

    2021

    On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators

    Authors
    Santos, T; Paulino, N; Bispo, J; Cardoso, JMP; Ferreira, JC;

    Publication
    International Conference on Field-Programmable Technology, (IC)FPT 2021, Auckland, New Zealand, December 6-10, 2021

    Abstract

    2020

    A Dynamically Reconfigurable Dual-Waveform Baseband Modulator for Flexible Wireless Communications

    Authors
    Ferreira, ML; Ferreira, JC;

    Publication
    JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY

    Abstract
    In future wireless communication systems, several radio access technologies will coexist and interwork to provide a great variety of services with different requirements. Thus, the design of flexible and reconfigurable hardware is a relevant topic in wireless communications. The combination of high performance, programmability and flexibility makes Field-programmable gate array a convenient platform to design such systems, especially for base stations. This paper describes a dynamically reconfigurable baseband modulator for Orthogonal Frequency Division Multiplexing and Filter-bank Multicarrier modulation waveforms implemented on a Virtex-7 board. The design features Dynamic Partial Reconfiguration (DPR) capabilities to adapt its mode of operation at run-time and is compared with a functionally equivalent static multi-mode design regarding processing throughput, resource utilization, functional density and power consumption. The DPR-based design implementation reserves about half the resources used by static multi-mode counterpart. Consequently, the baseband processing dynamic power consumption observed in the DPR-based design is between 26 mW to 90 mW lower than in the static multi-mode design, representing a dynamic power reduction between 13% to 52%. The worst-case DPR latency measured was 1.051 ms, while the DPR energy overhead is below 1.5 mJ. Considering latency requirements for modern wireless standards and power consumption constraints for commercial base stations, the DPR application is shown to be valuable in multi-standard and multi-mode systems, as well as in scenarios such as multiple-input and multiple-output or dynamic spectrum aggregation.

    Supervised
    thesis

    2021

    Energy-efficient, dynamically reconfigurable hardware architectures for long short-term memories

    Author
    Daniel Miranda Silva Malafaia Granhão

    Institution
    UP-FEUP

    2021

    Runtime Management of Heterogeneous Compute Resources in Embedded Systems

    Author
    Luís Miguel Mendes Pimentel Alves de Sousa

    Institution
    UP-FEUP

    2021

    A QEMU-based Approach to Hardware-Assisted Virtualization

    Author
    Pedro Casais da Silva e Sousa Gonçalves

    Institution
    UP-FEUP

    2021

    Study and Implementation of a Hardware Cross Architecture Virtualization Accelerator

    Author
    João Pedro Vigário Garrido

    Institution
    UP-FEUP

    2021

    Implementação de sistema de “beamforming” em FPGA para comunicação com satélites

    Author
    Telmo Francisco da Costa Soares

    Institution
    UP-FEUP