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About

About

I received the Ph.D. degree in Electrical and  Computer Engineering from the University of Porto (Portugal) in 2001. I 'm currently an assistant professor with the Faculty of Engineering, University of Porto, and a senior researcher at INESC TEC. I'm a member of IEEE, ACM and Euromicro.


My research interests center around the design of dedicated digital systems for complex and demanding embedded applications. I'm particularly interested in three areas:

  • Design of self-adaptive digital systems
  • FPGA-based reconfigurable computing
  • Hardware acceleration of embedded systems
  • Some concrete research topics are:

    • dynamic reconfiguration of FPGAs
    • generation of FPGA configurations at run-time
    • fast physical synthesis for digital circuits
    • virtual programmable hardware architectures
    • transparent task migration from software→hardware

    Interest
    Topics
    Details

    Details

    005
    Publications

    2019

    An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios

    Authors
    Ferreira, ML; Ferreira, JC;

    Publication
    ELECTRONICS

    Abstract
    The next evolution in cellular communications will not only improve upon the performance of previous generations, but also represent an unparalleled expansion in the number of services and use cases. One of the foundations for this evolution is the design of highly flexible, versatile, and resource-/power-efficient hardware components. This paper proposes and evaluates an FPGA-oriented baseband processing architecture suitable for communication scenarios such as non-contiguous carrier aggregation, centralized Cloud Radio Access Network (C-RAN) processing, and 4G/5G waveform coexistence. Our system is upgradeable, resource-efficient, cost-effective, and provides support for three 5G waveform candidates. Exploring Dynamic Partial Reconfiguration (DPR), the proposed architecture expands the design space exploration beyond the available hardware resources on the Zynq xc7z020 through hardware virtualization. Additionally, Dynamic Frequency Scaling (DFS) allows for run-time adjustment of processing throughput and reduces power consumption up to 88%. The resource overhead for DPR and DFS is residual, and the reconfiguration latency is two orders of magnitude below the control plane latency requirements proposed for 5G communications.

    2019

    Dynamic Partial Reconfiguration of Customized Single-Row Accelerators

    Authors
    Cardanha Paulino, NM; Ferreira, JC; Cardoso, JMP;

    Publication
    IEEE Trans. VLSI Syst.

    Abstract

    2019

    Dynamic Partial Reconfiguration of Customized Single-Row Accelerators

    Authors
    Paulino, NMC; Ferreira, JC; Cardoso, JMP;

    Publication
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

    Abstract

    2019

    Wearable sensor networks for human gait

    Authors
    Machado da Silva, J; Derogarian, F; Canas Ferreira, J; Grade Tavares, V;

    Publication
    Wearable Technologies and Wireless Body Sensor Networks for Healthcare

    Abstract

    2019

    A precise low power and hardware-efficient time synchronization method for wearable systems

    Authors
    Derogarian, F; Canas Ferreira, J; Grade Tavares, V; Machado da Silva, J; Velez, FJ;

    Publication
    Wearable Technologies and Wireless Body Sensor Networks for Healthcare

    Abstract

    Supervised
    thesis

    2017

    Configurable coarse-grained array architecture for processing of biological signals

    Author
    João Pedro Sauvarin Lopes

    Institution
    UP-FEUP

    2017

    FPGA implementation of a baseband processor for FBMC transmission

    Author
    Miguel Nuno Marques Vaz de Carvalho

    Institution
    UP-FEUP

    2017

    "Profiling" por hardware em tempo real para sistemas embebidos

    Author
    Rui Miguel Almeida Alves

    Institution
    UP-FEUP

    2017

    Evolução da componente algorítmica de cálculo de rotas do Move-Me

    Author
    André Pedro Deus Pinheiro

    Institution
    UP-FEUP

    2017

    Implementação em FPGA de um conversor HDMI para transmissão em série de alta velocidade

    Author
    Ana Marisa Oliveira Barbosa

    Institution
    UP-FEUP