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Sobre

Sobre

Recebi o doutoramento em Engenharia Electrotécnica e de Computadores pela Universidade do Porto (Portugal) em 2001. Atualmente sou professor auxiliar na Faculdade de Engenharia da Universidade do Porto e investigador sénior do INESC TEC. Sou membro de IEEE, ACM e Euromicro.

Os meus interesses de investigação centram-se no projeto de sistemas digitais dedicados para aplicações complexas e exigentes. Estou particularmente interessado em três áreas:

1. Concepção de sistemas digitais auto-adaptáveis
2. Computação reconfigurável baseada em FPGA
3. Aceleração de hardware para sistemas embarcados (com ênfase em sistemas de telecomunicações e bio-médicos)

Alguns tópicos concretos de investigação são:
     - Reconfiguração dinâmica de FPGAs
     - Geração de configurações FPGA em tempo de execução
     - Síntese física rápida para circuitos digitais
     - Arquiteturas virtuais de hardware programável
     - Migração de tarefas transparente de software → hardware

Tópicos
de interesse
Detalhes

Detalhes

005
Publicações

2021

Transparent Control Flow Transfer between CPU and Accelerators for HPC

Autores
Granhao, D; Ferreira, JC;

Publicação
ELECTRONICS

Abstract
Heterogeneous platforms with FPGAs have started to be employed in the High-Performance Computing (HPC) field to improve performance and overall efficiency. These platforms allow the use of specialized hardware to accelerate software applications, but require the software to be adapted in what can be a prolonged and complex process. The main goal of this work is to describe and evaluate mechanisms that can transparently transfer the control flow between CPU and FPGA within the scope of HPC. Combining such a mechanism with transparent software profiling and accelerator configuration could lead to an automatic way of accelerating regular applications. In this work, a mechanism based on the ptrace system call is proposed, and its performance on the Intel Xeon+FPGA platform is evaluated. The feasibility of the proposed approach is demonstrated by a working prototype that performs the transparent control flow transfer of any function call to a matching hardware accelerator. This approach is more general than shared library interposition at the cost of a small time overhead in each accelerator use (about 1.3ms in the prototype implementation).

2021

A Binary Translation Framework for Automated Hardware Generation

Autores
Paulino, N; Bispo, J; Ferreira, JC; Cardoso, JMP;

Publicação
IEEE MICRO

Abstract

2021

Pedagogical Innovation in Pandemic Times: The Experience of a Microprocessor Programming Course

Autores
Lima, B; Granhão, D; Araújo, AJ; Ferreira, JC;

Publicação
2021 4th International Conference of the Portuguese Society for Engineering Education, CISPEE 2021

Abstract

2021

On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators

Autores
Santos, T; Paulino, N; Bispo, J; Cardoso, JMP; Ferreira, JC;

Publicação
2021 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (ICFPT)

Abstract

2020

A Dynamically Reconfigurable Dual-Waveform Baseband Modulator for Flexible Wireless Communications

Autores
Ferreira, ML; Ferreira, JC;

Publicação
JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY

Abstract
In future wireless communication systems, several radio access technologies will coexist and interwork to provide a great variety of services with different requirements. Thus, the design of flexible and reconfigurable hardware is a relevant topic in wireless communications. The combination of high performance, programmability and flexibility makes Field-programmable gate array a convenient platform to design such systems, especially for base stations. This paper describes a dynamically reconfigurable baseband modulator for Orthogonal Frequency Division Multiplexing and Filter-bank Multicarrier modulation waveforms implemented on a Virtex-7 board. The design features Dynamic Partial Reconfiguration (DPR) capabilities to adapt its mode of operation at run-time and is compared with a functionally equivalent static multi-mode design regarding processing throughput, resource utilization, functional density and power consumption. The DPR-based design implementation reserves about half the resources used by static multi-mode counterpart. Consequently, the baseband processing dynamic power consumption observed in the DPR-based design is between 26 mW to 90 mW lower than in the static multi-mode design, representing a dynamic power reduction between 13% to 52%. The worst-case DPR latency measured was 1.051 ms, while the DPR energy overhead is below 1.5 mJ. Considering latency requirements for modern wireless standards and power consumption constraints for commercial base stations, the DPR application is shown to be valuable in multi-standard and multi-mode systems, as well as in scenarios such as multiple-input and multiple-output or dynamic spectrum aggregation.

Teses
supervisionadas

2021

Energy-efficient, dynamically reconfigurable hardware architectures for long short-term memories

Autor
Daniel Miranda Silva Malafaia Granhão

Instituição
UP-FEUP

2021

Redução de herbicidas de pré-emergência na cultura do milho (Zea mays L.) combinando estratégias de aplicação em faixa com meios mecânicos numa ótica de agricultura de precisão

Autor
Henrique Ramos Silva

Instituição
UP-FCUP

2021

Otimização de sistemas de autoconsumo baseados no potencial eólico para edifícios de elevada altura

Autor
Carlos José Seabra Costa Oliveira

Instituição
UTAD

2021

A QEMU-based Approach to Hardware-Assisted Virtualization

Autor
Pedro Casais da Silva e Sousa Gonçalves

Instituição
UP-FEUP

2021

MELHORIA DO PROCESSO DE MONOTORIZAÇÃO E CONTROLO DA PRODUÇÃO NA INDÚSTRIA CORTICEIRA

Autor
JOÃO CARLOS PAIS SANTOS

Instituição
IPP-ISEP