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Sobre
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Sobre

Recebi o doutoramento em Engenharia Electrotécnica e de Computadores pela Universidade do Porto (Portugal) em 2001. Atualmente sou professor auxiliar na Faculdade de Engenharia da Universidade do Porto e investigador sénior do INESC TEC. Sou membro de IEEE, ACM e Euromicro.

Os meus interesses de investigação centram-se no projeto de sistemas digitais dedicados para aplicações complexas e exigentes. Estou particularmente interessado em três áreas:

1. Concepção de sistemas digitais auto-adaptáveis
2. Computação reconfigurável baseada em FPGA
3. Aceleração de hardware para sistemas embarcados (com ênfase em sistemas de telecomunicações e bio-médicos)

Alguns tópicos concretos de investigação são:
     - Reconfiguração dinâmica de FPGAs
     - Geração de configurações FPGA em tempo de execução
     - Síntese física rápida para circuitos digitais
     - Arquiteturas virtuais de hardware programável
     - Migração de tarefas transparente de software → hardware

Tópicos
de interesse
Detalhes

Detalhes

005
Publicações

2020

A Dynamically Reconfigurable Dual-Waveform Baseband Modulator for Flexible Wireless Communications

Autores
Ferreira, ML; Ferreira, JC;

Publicação
JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY

Abstract
In future wireless communication systems, several radio access technologies will coexist and interwork to provide a great variety of services with different requirements. Thus, the design of flexible and reconfigurable hardware is a relevant topic in wireless communications. The combination of high performance, programmability and flexibility makes Field-programmable gate array a convenient platform to design such systems, especially for base stations. This paper describes a dynamically reconfigurable baseband modulator for Orthogonal Frequency Division Multiplexing and Filter-bank Multicarrier modulation waveforms implemented on a Virtex-7 board. The design features Dynamic Partial Reconfiguration (DPR) capabilities to adapt its mode of operation at run-time and is compared with a functionally equivalent static multi-mode design regarding processing throughput, resource utilization, functional density and power consumption. The DPR-based design implementation reserves about half the resources used by static multi-mode counterpart. Consequently, the baseband processing dynamic power consumption observed in the DPR-based design is between 26 mW to 90 mW lower than in the static multi-mode design, representing a dynamic power reduction between 13% to 52%. The worst-case DPR latency measured was 1.051 ms, while the DPR energy overhead is below 1.5 mJ. Considering latency requirements for modern wireless standards and power consumption constraints for commercial base stations, the DPR application is shown to be valuable in multi-standard and multi-mode systems, as well as in scenarios such as multiple-input and multiple-output or dynamic spectrum aggregation.

2020

Parallel Implementation of K-Means Algorithm on FPGA

Autores
Dias, LA; Ferreira, JC; Fernandes, MAC;

Publicação
IEEE ACCESS

Abstract
The K-means algorithm is widely used to find correlations between data in different application domains. However, given the massive amount of data stored, known as Big Data, the need for high-speed processing to analyze data has become even more critical, especially for real-time applications. A solution that has been adopted to increase the processing speed is the use of parallel implementations on FPGA, which has proved to be more efficient than sequential systems. Hence, this paper proposes a fully parallel implementation of the K-means algorithm on FPGA to optimize the system & x2019;s processing time, thus enabling real-time applications. This proposal, unlike most implementations proposed in the literature, even parallel ones, do not have sequential steps, a limiting factor of processing speed. Results related to processing time (or throughput) and FPGA area occupancy (or hardware resources) were analyzed for different parameters, reaching performances higher than 53 millions of data points processed per second. Comparisons to the state of the art are also presented, showing speedups of more than over a partially serial implementation.

2020

Improving performance and energy consumption in embedded systems via binary acceleration: A survey

Autores
Paulino, N; Ferreira, JC; Cardoso, JMP;

Publicação
ACM Computing Surveys

Abstract
The breakdown of Dennard scaling has resulted in a decade-long stall of the maximum operating clock frequencies of processors. To mitigate this issue, computing shifted to multi-core devices. This introduced the need for programming flows and tools that facilitate the expression of workload parallelism at high abstraction levels. However, not all workloads are easily parallelizable, and the minor improvements to processor cores have not significantly increased single-threaded performance. Simultaneously, Instruction Level Parallelism in applications is considerably underexplored. This article reviews notable approaches that focus on exploiting this potential parallelism via automatic generation of specialized hardware from binary code. Although research on this topic spans over more than 20 years, automatic acceleration of software via translation to hardware has gained new importance with the recent trend toward reconfigurable heterogeneous platforms. We characterize this kind of binary acceleration approach and the accelerator architectures on which it relies. We summarize notable state-of-the-art approaches individually and present a taxonomy and comparison. Performance gains from 2.6× to 5.6× are reported, mostly considering bare-metal embedded applications, along with power consumption reductions between 1.3× and 3.9×. We believe the methodologies and results achievable by automatic hardware generation approaches are promising in the context of emergent reconfigurable devices. © 2020 Association for Computing Machinery.

2019

An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios

Autores
Ferreira, ML; Ferreira, JC;

Publicação
ELECTRONICS

Abstract
The next evolution in cellular communications will not only improve upon the performance of previous generations, but also represent an unparalleled expansion in the number of services and use cases. One of the foundations for this evolution is the design of highly flexible, versatile, and resource-/power-efficient hardware components. This paper proposes and evaluates an FPGA-oriented baseband processing architecture suitable for communication scenarios such as non-contiguous carrier aggregation, centralized Cloud Radio Access Network (C-RAN) processing, and 4G/5G waveform coexistence. Our system is upgradeable, resource-efficient, cost-effective, and provides support for three 5G waveform candidates. Exploring Dynamic Partial Reconfiguration (DPR), the proposed architecture expands the design space exploration beyond the available hardware resources on the Zynq xc7z020 through hardware virtualization. Additionally, Dynamic Frequency Scaling (DFS) allows for run-time adjustment of processing throughput and reduces power consumption up to 88%. The resource overhead for DPR and DFS is residual, and the reconfiguration latency is two orders of magnitude below the control plane latency requirements proposed for 5G communications.

2019

Dynamic Partial Reconfiguration of Customized Single-Row Accelerators

Autores
Paulino, NMC; Ferreira, JC; Cardoso, JMP;

Publicação
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Abstract

Teses
supervisionadas

2019

Transparent control flow transfer between CPU and Intel FPGAs

Autor
Daniel Miranda Silva Malafaia Granhão

Instituição
UP-FEUP

2019

Gerador de padrões de vídeo UHD utilizando HDL (Verilog)

Autor
Júnio Duarte Lopes Parente

Instituição
UP-FEUP

2019

Reconfigurable FPGA-Based Baseband Processor for Multi-mode Spectrum Aggregation

Autor
Mário Lopes Ferreira

Instituição
UP-FEUP

2019

Accelerating the training of convolutional neural network

Autor
Afonso de Sá Reis

Instituição
UP-FEUP

2018

Study and Implementation of Optimized Solutions for Re-Configurable Logic over ASIC Design Flow

Autor
Ricardo Azevedo Araújo

Instituição
UP-FEUP