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About

About

I received B.Sc. in Electric Engineering from Universidade Federal do Paraná (2011) and successfully completed the M.Sc in Computer Engineering from Universidade Federal do Rio Grande (2015), where I also worked as a Substitute Professor. Completed the IC-Brazil Program (2016). Nowadays, I am a Researcher at INESC TEC. I have experience in Electric Engineering, acting on the following subjects: Microelectronics and Digital IC Design.

Interest
Topics
Details

Details

002
Publications

2018

Design and Evaluation of a Low Power CGRA Accelerator for Biomedical Signal Processing

Authors
Avelar, HH; Ferreira, JC;

Publication
21st Euromicro Conference on Digital System Design, DSD 2018, Prague, Czech Republic, August 29-31, 2018

Abstract
This work presents the design and analysis of a biological signal processing accelerator, including an interface controller and memory subsystem for a low-power CGRA. The controller design supports several operation modes, which can perform several applications when paired with the CGRA reconfiguration capabilities. Physical synthesis shows that the controller introduces only a 6 percent area and power overhead compared to the CGRA core, while allowing independent processing of inner loops at high frequencies and the exploitation of pipelining and parallelism. In-depth power analysis based on layout information was performed, including an evaluation of the use of power gating techniques. A practical case study (ECG signal processing) was also evaluated. © 2018 IEEE.

Supervised
thesis

2021

Implementação de sistema de “beamforming” em FPGA para comunicação com satélites

Author
Telmo Francisco da Costa Soares

Institution
UP-FEUP