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Research Opportunity
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Research Opportunity

Digital Electronics, Microprocessors, Heterogeneous Systems


Work description

- Implement the behavior of a RISC-V processor using C/C++ - Check the feasibility of using the developed code as a RISC-V simulator - Check the feasibility of using the developed code for hardware implementation of a RISC-V processor, using HLS tools - Compare the implementation with state-of-the-art RISC-V simulators or cores - Optionally, add to the implementation the ability to specify extensions to the base instruction set

Academic Qualifications

Enrolment in Licenciatura or MSc in Electronics Engineering, or similar

Minimum profile required

- programming experience in C/C++- experience with FPGAs and/or hardware accelerators

Preference factors

- high-Level-Synthesis experience - RISC-V experience

Application Period

Since 18 Apr 2024 to 03 May 2024



Telecommunications and Multimedia

Scientific Advisor

Nuno Miguel Paulino