Computing, Electronics and Digital Systems
[Open soon]
Work description
? Familiarization with reference CGRA simulators (e.g., OpenEdgeCGRA, or designs from project partners), and with the current version of the custom instruction set; ? Review and improve the instruction set for controlling the CGRA; ? Implement the hardware (or simulation-level model) necessary for interpreting a “custom” instruction set that allows RISC-V to control the coprocessor directly; ? Collaboration in the writing of a scientific article to disseminate the results.
Academic Qualifications
? Bachelor's degree or enrollment in a master's degree in electrical engineering, computer science, or a related field;
Minimum profile required
? Experience in HDL and C++? Fluency in English (written and spoken)
Preference factors
? Experience in RISC-V ? Experience in FPGA or heterogeneous systems ? Fluent in Portuguese and English (written and spoken)
Application Period
Since 20 Aug 2026 to 03 Sep 2026
[Open soon]
Centre
Telecommunications and Multimedia