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About

My educational background includes Ph.D, M.Sc. and B.Sc., degrees in Computer Science from the Faculty of Sciences of the University of Porto. I'm currently a Post-Doctoral researcher working in INESCTEC-CRACS and funded by the FCT - Fundação para a Ciência e Tecnologia. My research interests lie on parallel and concurrent programming, and tabling mechanisms applied to Logic Programming.

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Details

Details

  • Name

    Miguel Gonçalves Areias
  • Cluster

    Computer Science
  • Role

    Researcher
  • Since

    16th May 2011
Publications

2020

A compression-based design for higher throughput in a lock-free hash map

Authors
Moreno, P; Areias, M; Rocha, R;

Publication
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Abstract
Lock-free implementation techniques are known to improve the overall throughput of concurrent data structures. A hash map is an important data structure used to organize information that must be accessed frequently. A key role of a hash map is the ability to balance workloads by dynamically adjusting its internal data structures in order to provide the fastest possible access to the information. This work extends a previous lock-free hash map design to also support lock-free compression. The main goal is to significantly reduce the depth of the internal hash levels within the hash map, in order to minimize cache misses and increase the overall throughput. To materialize our design, we redesigned the existent search, insert, remove and expand operations in order to maintain the lock-freedom property of the whole design. Experimental results show that lock-free compression effectively improves the search operation and, in doing so, it outperforms the previous design, which was already quite competitive when compared against the concurrent hash map design supported by Intel. © Springer Nature Switzerland AG 2020.

2019

Multi-dimensional lock-free arrays for multithreaded mode-directed tabling in Prolog

Authors
Areias, M; Rocha, R;

Publication
Concurrency and Computation: Practice and Experience

Abstract

2019

Memory reclamation methods for lock-free hash tries

Authors
Moreno, P; Areias, M; Rocha, R;

Publication
Proceedings - Symposium on Computer Architecture and High Performance Computing

Abstract
Hash tries are a trie-based data structure with nearly ideal characteristics for the implementation of hash maps. Starting from a particular lock-free hash map data structure, named Lock-Free Hash Tries (LFHT), we focus on solving the problem of memory reclamation without losing the lockfreedom property. We propose an approach that explores the characteristics of the LFHT structure in order to achieve efficient memory reclamation with low and well-defined memory bounds. Experimental results show that our approach obtains better results when compared with other state-of-the-art memory reclamation methods and provides a competitive and scalable hash map implementation, if compared to lock-based implementations. © 2019 IEEE.

2018

Table space designs for implicit and explicit concurrent tabled evaluation

Authors
Areias, M; Rocha, R;

Publication
THEORY AND PRACTICE OF LOGIC PROGRAMMING

Abstract
One of the main advantages of Prolog is its potential for the implicit exploitation of parallelism and, as a high-level language, Prolog is also often used as a means to explicitly control concurrent tasks. Tabling is a powerful implementation technique that overcomes some limitations of traditional Prolog systems in dealing with recursion and redundant subcomputations. Given these advantages, the question that arises is if tabling has also the potential for the exploitation of concurrency/parallelism. On one hand, tabling still exploits a search space as traditional Prolog but, on the other hand, the concurrent model of tabling is necessarily far more complex, since it also introduces concurrency on the access to the tables. In this paper, we summarize Yap's main contributions to concurrent tabled evaluation and we describe the design and implementation challenges of several alternative table space designs for implicit and explicit concurrent tabled evaluation that represent different tradeoffs between concurrency and memory usage. We also motivate for the advantages of using fixed-size and lock freedata structures, elaborate on the key role that the engine's memory allocator plays on such environments, and discuss how Yap's mode-directed tabling support can be extended to concurrent evaluation. Finally, we present our future perspectives toward an efficient and novel concurrent framework which integrates both implicit and explicit concurrent tabled evaluation in a single Prolog engine.

2018

On Extending a Fixed Size, Persistent and Lock-Free Hash Map Design to Store Sorted Keys

Authors
Areias, M; Rocha, R;

Publication
2018 IEEE INT CONF ON PARALLEL & DISTRIBUTED PROCESSING WITH APPLICATIONS, UBIQUITOUS COMPUTING & COMMUNICATIONS, BIG DATA & CLOUD COMPUTING, SOCIAL COMPUTING & NETWORKING, SUSTAINABLE COMPUTING & COMMUNICATIONS

Abstract
Searching is a crucial time-consuming part of many programs, and using a good search method instead of a bad one often leads to a substantial increase in performance. Hash tries are a trie-based data structure with nearly ideal characteristics for the implementation of hash maps. In this paper, we present a novel, simple and concurrent hash map design that fully supports the concurrent search, insert and remove operations on hash tries designed to store sorted keys. To the best of our knowledge, our design is the first concurrent hash map design that puts together the following characteristics: (i) use fixed size data structures; (ii) use persistent memory references; (iii) be lock-free; and (iv) store sorted keys. Experimental results show that our design is quite competitive when compared against other state-of-the-art designs implemented in Java.