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MSc and PhD in Electrical Engineering, Syracuse University, NY, USA, (1979 and 1983).

Licenciatura in Electrical Engineering, University of Porto (1973).



Full Professor, Faculty of Engineering, University of Porto (FEUP), Department of Electrical and Computer Engineering, since 2000. Retired (Jubilado) in October, 2021.

Taught in the areas of Microelectronics (VLSI), Design and Test of Digital and Mixed-signal integrated circuits, Digital System Design and Computer Architecture at FEUP and in Sysracuse University (Visiting Assistant Professor, 1986/87). Supervised 6 Doctorates.

Research and Development

Researcher at INESC TEC (, since 1988, where he founded the CAD and Microectronics Group, which he led until 2001. He was responsible for the participation of the Group in several international R&D projects, with european universities and industrial partners.

  • ASSOCIATE – Advanced Solutions for SoC Innovative Testing in Europe (2001-2004);
  • DYNAD – Digital/Analog Converter Testing (1998-2001);
  • MAGIA – Dedicated HW for an Industrial Textile Nesting Application (1998-2000);
  • AIPAC – ASIC-based System Design and Integration (1995-1996);
  • CHIPSHOP – Low Cost IC Prototyping Services for European SMEs;
  • ARTEMIS – Mixed-Signal Testing (1992-1995);
  • AICI – ESPRIT Special Action for Microelectronics in Portugal (1990-1995);
  • BST – Boundary Scan Test (1989-1992)

Responsible for advanced training actions in Microelectronics, for and with companies like ChipIdea, MIPS, SIEMENS, Infineon and Qimonda.

Visiting Research Associate in the CASE Center, Syracuse University, (1986/1987) and R&D Engineer in the Electronics Laboratory (ELab), General Electric Company, Syracuse, NY, USA (1983-84).

List of publications available in


University management and extension

Director of PDEEC, the Doctoral Program in Electrical and Computer Engineering of FEUP (2016-2021).

Director of PDEPP, the Doctoral Program in Engineering and Public Policy of FEUP (2011-2016), which he helped creating.

President of the Council of Representatives (Conselho de Representantes) of FEUP (2014-2016). 

Director of the Department of Electrical and Computer Engineering (DEEC) of FEUP (2001 – 2010).

Director of the Undergraduate Program (Licenciatura) in Electrical and Computer Engineering of FEUP (1992-2001). 

President of the Pedagogical Council of FEUP (1993-1999).

National Delegate, representing the Portuguese Government in the Management Committees of all the European R&D Programs in Information Technologies, since ESPRIT (1994-2001), including the 6th and 7th Framework Programs (2001-2006 e 2007-2014) and Horizon 2020 (2014-2020).

Member of the Program Committees and Steering Committees of International Conferences (DCIS, EUROMICRO DSD, ICECS, ISQED). 

General Chair: EUROMICRO Conference on Digital System Design (DSD 2005 and 2015) and the International Conference on the Design of Circuits and Integrated Systems (DCIS 2001).

Guest Editor of the International Journal of Embedded Hardware Design (MICPRO), Elsevier, and of the International Journal of Analog Integrated Circuits and Signal Processing, Kluwer. 

Member of the Board of Directors of EUROMICRO ( and Senior Member of IEEE.

Professor Emeritus of the University of Porto, 2023.



  • Name

    José Silva Matos
  • Role

    Research Coordinator
  • Since

    01st January 1985


Scalable hardware architecture for disparity map computation and object location in real-time

Santos, PM; Ferreira, JC; Matos, JS;


We present the disparity map computation core of a hardware system for isolating foreground objects in stereoscopic video streams. The operation is based on the computation of dense disparity maps using block-matching algorithms and two well-known metrics: sum of absolute differences and Census transform. Two sets of disparity maps are computed by taking each of the images as reference so that a consistency check can be performed to identify occluded pixels and eliminate spurious foreground pixels. Taking advantage of parallelism, the proposed architecture is highly scalable and provides numerous degrees of adjustment to different application needs, performance levels and resource usage. A version of the system for 640 x 480 images and a maximum disparity of 135 pixels was implemented in a system based on a Xilinx Virtex II-Pro FPGA and two cameras with a frame rate of 25 fps (less than the maximum supported frame rate of 40 fps on this platform). Implementation of the same system on a Virtex-5 FPGA is estimated to achieve 80 fps, while a version with increased parallelism is estimated to run at 140 fps (which corresponds to the calculation of more than 5.9 x 10(9) disparity-pixels per second).


From Boolean algebra to processor architecture and assembly programming in one semester

Matos, JS; Alves, JC; Mendonca, HS; Araujo, AJ;

Proceedings of the 2014 29th Conference on Design of Circuits and Integrated Systems, DCIS 2014

The paper presents the approach followed at the Faculty of Engineering of the University of Porto, to introduce design automation tools and structured design techniques in the first course on digital system design of our Integrated Master in Electrical and Computer Engineering. Digital Systems Laboratory is an introductory course on digital design, with the classical task of teaching Boolean algebra and combinational and sequential circuit design, using gates, flip-flops and medium complexity components/function blocks like counters and shift-registers. The need to cope with new curriculum requirements and modern digital design demands, motivated an extensive reformulation of the course contents and organization, leading to the introduction of the use of hardware description languages and synthesis tools, in order to implement small systems, of increasingly complex nature, on an FPGA platform. At the same time its coverage was extended to include low-level processor architecture issues, and to teach assembly programming for the MIPS processor. The paper describes how this reformulation was carried out. It presents the course contents and timeline, and discusses the main choices that were made. The paper also describes the laboratory experiments that were developed and discusses some of the challenges and results obtained so far. © 2014 IEEE.


Estimation of analogue-to-digital converter's signal-to-noise plus distortion ratio using the code histogram method

Mendonca, HS; da Silva, JM; Matos, JS;


A procedure is proposed to estimate an analogue-to-digital converter's signal-to-noise plus distortion ratio using the histogram method. The procedure provides results that are in close agreement with the ones obtained with the spectral analysis and sinewave fitting methods. It is shown that the errors obtained by using former implementations of the histogram method are due to not considering the input stimulus probability density function, and it is shown how these errors can be rectified.


Design of circuits and integrated systems

Teixeira, JP; Matos, JS; Tomas, J; Teixeira, IC;




A processor for testing mixed-signal cores in System-on-Chip

Duarte, F; da Silva, JM; Alves, JC; Pinho, GA; Matos, JS;

DSD 2005: 8th Euromicro Conference on Digital System Design, Proceedings

This paper describes the design of a processor specific for testing cores embedded in system-on-chip. This processor which can be implemented within a system's reconfigurable area, shall be responsible for scheduling and control test operations and perform preliminary data processing, as well as to provide the interface with an external tester Building these test operations on-chip allows for simplifying external tester interface and to reduce testing time. The testing procedure and the infrastructure required to test an AID converter is described as an example.