Cookies Policy
We use cookies to improve our site and your experience. By continuing to browse our site you accept our cookie policy. Find out More
Close
  • Menu
About

About

Full Professor, Department of Electrical and Computer Engineering (DEEC), Faculty of Engineering of the University of Porto (FEUP). Areas of Microelectronics and Digital System Design.

President of the Council of Representatives of FEUP.  Member of the University Senate and of the Pedagogical Council of FEUP.

Director of the Doctoral Program in Electrical and Computer Engineering (PDEEC) and of the Doctoral Program in Engineering and Public Policy (PDEPP), of FEUP.

National Delegate and member of the Information and Communication Technologies Committee (ICTC), of the 8th Framework Programa in Research, Innovation and Development (Horizon 2020) of the European Union.

Member of the Board of Directors of Euromicro (www.euromicro.org) and of the Steering Committee of DSD (Euromicro Conference on Digital System Design) and DCIS (International Conference on the Design of Circuits and Integrated Systems).  Senior Member of IEEE.

Interest
Topics
Details

Details

Publications

2016

Scalable hardware architecture for disparity map computation and object location in real-time

Authors
Santos, PM; Ferreira, JC; Matos, JS;

Publication
JOURNAL OF REAL-TIME IMAGE PROCESSING

Abstract
We present the disparity map computation core of a hardware system for isolating foreground objects in stereoscopic video streams. The operation is based on the computation of dense disparity maps using block-matching algorithms and two well-known metrics: sum of absolute differences and Census transform. Two sets of disparity maps are computed by taking each of the images as reference so that a consistency check can be performed to identify occluded pixels and eliminate spurious foreground pixels. Taking advantage of parallelism, the proposed architecture is highly scalable and provides numerous degrees of adjustment to different application needs, performance levels and resource usage. A version of the system for 640 x 480 images and a maximum disparity of 135 pixels was implemented in a system based on a Xilinx Virtex II-Pro FPGA and two cameras with a frame rate of 25 fps (less than the maximum supported frame rate of 40 fps on this platform). Implementation of the same system on a Virtex-5 FPGA is estimated to achieve 80 fps, while a version with increased parallelism is estimated to run at 140 fps (which corresponds to the calculation of more than 5.9 x 10(9) disparity-pixels per second).

2014

From Boolean algebra to processor architecture and assembly programming in one semester

Authors
Matos, JS; Alves, JC; Mendonca, HS; Araujo, AJ;

Publication
Proceedings of the 2014 29th Conference on Design of Circuits and Integrated Systems, DCIS 2014

Abstract
The paper presents the approach followed at the Faculty of Engineering of the University of Porto, to introduce design automation tools and structured design techniques in the first course on digital system design of our Integrated Master in Electrical and Computer Engineering. Digital Systems Laboratory is an introductory course on digital design, with the classical task of teaching Boolean algebra and combinational and sequential circuit design, using gates, flip-flops and medium complexity components/function blocks like counters and shift-registers. The need to cope with new curriculum requirements and modern digital design demands, motivated an extensive reformulation of the course contents and organization, leading to the introduction of the use of hardware description languages and synthesis tools, in order to implement small systems, of increasingly complex nature, on an FPGA platform. At the same time its coverage was extended to include low-level processor architecture issues, and to teach assembly programming for the MIPS processor. The paper describes how this reformulation was carried out. It presents the course contents and timeline, and discusses the main choices that were made. The paper also describes the laboratory experiments that were developed and discusses some of the challenges and results obtained so far. © 2014 IEEE.

2008

Estimation of ADC's SINAD after the Code Histogram Method

Authors
Hélio Sousa Mendonça; José Machado da Silva; José Silva Matos

Publication
IET Journal on Science - IET Journal on Science, vol.2, no.2, pp.96-99

Abstract

2005

A processor for testing mixed-signal cores in System-on-Chip

Authors
Francisco Xavier Fernandes Duarte; José Machado da Silva; José Carlos Alves; José da Silva Matos; António Gabriel Pinho

Publication
DSD'2005 - 8th EUROMICRO Conference on Digital System Design, Porto, Portugal

Abstract

2004

A Wrapper for Testing Analogue to Digital Converters Cores in SoCs

Authors
Joana Azevedo Braga; José Machado da Silva; José Carlos Alves; José da Silva Matos

Publication
ETS'04 - 9th IEEE European Test Symposium, Ajaccio, Corsega, França

Abstract