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Publicações

2003

An IEC 61131-3 compiler for the MatPLC

Autores
De Sousa, M; Carvalho, A;

Publicação
IEEE International Conference on Emerging Technologies and Factory Automation, ETFA

Abstract
We have implemented an IEC 61131-3 IL (Instruction List) and ST (Structured Text) compiler that will be part of an open source PLC. In doing so, several issues were found regarding the specification of the IL and ST languages, produced by the IEC (International Electrotechnical Commission ) standards body. The uncovered issues are discussed in this paper, and some changes to the standard are proposed. The architecture used in the compiler implementation is also outlined in the paper. © 2003 IEEE.

2003

Pulsed laser deposition of barium metaplumbate thin films for ferroelectric capacitors

Autores
Mardare, AI; Mardare, CC; Fernandes, JRA; Vilarinho, PM; Joanni, E;

Publicação
EUROPEAN PHYSICAL JOURNAL-APPLIED PHYSICS

Abstract
Barium metaplumbate thin films were deposited in situ by pulsed laser deposition on Si/SiO2/Ti/Pt substrates with a high deposition rate. The temperatures used ranged between 400 degreesC and 700 degreesC. As the deposition temperature was increased, the films assumed a strong (222) preferential orientation. This orientation of the electrodes was reflected on the PZT films, having a very big influence on their ferroelectric behavior. The PZT films made over BPO deposited at high temperature presented high values of remanent polarization (43 muC/cm(2)) but indications of high leakage currents could be observed in the hysteresis loops. By using BPO bottom electrodes, a 30% improvement in the fatigue behavior of PZT capacitors when compared with the normal platinum electrodes was observed.

2003

Bridging the gap between compilation and synthesis in the DEFACTO system

Autores
Diniz, P; Hall, M; Park, J; So, B; Ziegler, H;

Publicação
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Abstract
The DEFACTO project - a Design Environment For Adaptive Computing Technology - is a system that maps computations, expressed in high-level languages such as C, directly onto FPGA-based computing platforms. Major challenges are the inherent flexibility of FPGA hardware, capacity and timing constraints of the target FPGA devices, and accompanying speed-area trade-offs. To address these, DE-FACTO combines parallelizing compiler technology with behavioral VHDL synthesis tools, obtaining the complementary advantages of the compiler's high-level analyses and transformations and synthesis' binding, allocation and scheduling of low-level hardware resources. To guide the compiler in the search of a good solution, we introduce the notion of balance between the rates at which data is fetched from memory and accessed by the computation, combined with estimation from behavioral synthesis. Since FPGA-based designs offer the potential for optimizing memory-related operations, we have also incorporated the ability to exploit parallel memory accesses and customize memory access protocols into the compiler analysis. © Springer-Verlag Berlin Heidelberg 2003.

2003

Thermal behavior of Bragg gratings formed in germanosilicate fiber

Autores
Lima, MJN; Teixeira, ALJ; Frazao, O; Andre, PS; da Rocha, JRF;

Publicação
PHOTONICS, DEVICES, AND SYSTEMS II

Abstract
In this contribution we compare the thermal stability of type I and type IIa gratings written in germanosilicate fibers. We study and compare their central wavelengths drifts and variations of the maximum reflectivity with temperature. Also, two other important factors, the bandwidth and group delay characteristics are characterized, compared, and the differences justified, based on the gratings physical structure.

2003

Performance and area modeling of complete FPGA designs in the presence of loop transformations

Autores
Shesha Shayee, KR; Park, J; Diniz, PC;

Publicação
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Abstract
Selecting which program transformations to apply when mapping computations to FPGA-based architectures leads to prohibitively long design exploration cycles. An alternative is to develop fast, yet accurate, performance and area models to understand the impact and interaction of the transformations. In this paper we present a combined analytical performance and area modeling for complete FPGA designs in the presence of loop transformations. Our approach takes into account the impact of input/output memory bandwidth and memory interface resources, often the limiting factor in the effective implementation of these computations. Our preliminary results reveal that our modeling is very accurate allowing a compiler tool to quickly explore a very large design space resulting in the selection of a feasible high-performance design. © Springer-Verlag Berlin Heidelberg 2003.

2003

Growth and characterization of BaBi2Nb2O9 thin films made by RF-magnetron sputtering

Autores
Mazon, T; Joanni, E; Fernandes, JRA; Zaghete, MA; Cilense, M; Varela, JA;

Publicação
FERROELECTRICS

Abstract
The RF-magnetron sputtering technique has been used to deposit polycrystalline thin films of layered-structured ferroelectric BaBi2Nb2O9 (BBN). The XRD patterns for the films annealed at 700degreesC for 1 hour show the presence of the BBN phase as well as the BaNb2O6 secondary phase. A better crystallization of the BBN phase and an inhibition of the secondary phase is obtained with the increase of temperature. The surface of the prepared films was rather dense and smooth with no cracks. The 300 nm thick BBN thin films exhibited a room-temperature dielectric constant of about 779 with a dissipation factor of 0.09 at a frequency of 100 kHz.

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