Abstract
We report the use of Ada in the European research project Sol-Eu-Net. Ada was used in a web mining subproject, mainly for data preparation, and also for web system development. Open source Ada resources e.g. GNAT.Spitbol were used. Some such resources were modified, some created anew. XML and SQL were also used in association with Ada.

Abstract
In this paper, we describe a compilation system that automates much of the process of performance tuning that is currently done manually by application programmers interested in high performance. Due to the growing complexity of accurate performance prediction, our system incorporates empirical techniques to execute variants of code segments with representative data on the target architecture. In this paper, we discuss how empirical techniques and performance modeling can be effectively combined. We also discuss the role of historical information from prior runs, and programmer specifications supporting run-time adaptation. These techniques can be employed to alleviate some of the performance problems that lead to inefficiencies in key applications today: register pressure, cache conflict misses, and the trade-off between synchronization, parallelism and locality in SMPs. © 2003 IEEE.

Abstract
Digital image processing algorithms are a good match for direct implementation on FPGAs as current FPGA architectures can naturally match the fine grain parallelism in these applications. Typically, these algorithms are structured as a sequence of operations, expressed in high-level programming languages as tight loop nests. The loops usually define a shifting-window region over which the algorithm applies a simple localized operator (e.g., a differential gradient, or a min/max). In this research we focus on the development of fast, yet accurate performance and area modeling of complete FPGA designs that combine analytical, empirical and behavioral estimation techniques. We model the application of a set of important program transformations for image processing algorithms, namely loop unrolling, tiling, loop interchanging, loop fission and array privatization, and explore pipelined and non-pipelined execution modes. We take into consideration the impact of various transformations, in the presence of limited I/O resources like address generators and external memory data channels, on the performance of a complete design implemented in a FPGA based architecture. © 2003 IEEE.

Abstract
This paper investigates the nature of hazard analysis reuse over two case studies. Initially reuse in an existing safety argument is described. Argument structures within the hazard analysis are identified and the amount of verbatim reuse examined. A second study is concerned with how reuse changes as a result of tool support. In contrast to the first case, the defined arguments are more diverse - reuse has occurred but is less verbatim in nature. Tool supported argument adaptation has aided the customisation of the reused arguments. © Springer-Verlag Berlin Heidelberg 2003.

Abstract
FPGAs (field programmable gate arrays) have appealing features such as customizable internal and external bandwidth and the ability to exploit vast amounts of fine-grain parallelism. In this paper, we explore the applicability of these features in using FPGAs as smart memory engines for search and reorganization computations over spatial pointer-based data structures. The experimental results in this paper suggests that reconfigurable logic, when combined with the data reorganization, can lead to dramatic performance improvements of up to 20x over traditional computer architectures for pointer-based computations, traditionally not viewed as a good match for reconfigurable technologies. © 2003 IEEE.

Abstract
A simple method for crystallizing amorphous thin films was developed using platinum bottom electrodes as heating elements. A current was applied to chromel wires in contact with the platinum and the temperature was measured using a type K thermocouple. A proportional feedback algorithm was used for controlling the process. The optimum parameters for the temperature control were determined and applied to the crystallization of PZT thin films. The results obtained for a heat treatment at 650degreesC with a 15degreesC/s heating and cooling rate showed a pure perovskite phase; the ferroelectric properties were comparable with those from conventional heat treatment methods.