Abstract
This paper presents a architecture control and model identification of a onmi-Directional Mobile Robot It is divided into the three stages. Stage one proposes a procedure for dynamic model identification and control of the "motor + reduction + encoder" process of the Robot's Motors. Second, proposes the identification of a dynamic model for the whole mobile robot considering it as a multi-variable system. Third, presents a algorithm for perfect trajectory tracking of Omni-Directional Mobile Robots, based on restriction on motor's velocities. This algorithm combines the restriction on motor's velocities and the kinematic model of mobile robot to generate ideal drive velocities for the mobile robot to follow the trajectories correctly with the best possible performance.

Abstract
Current high-end Field-Programmable-Gate-Array (FPGA) parts offer a large number of configurable resources. These can be organized in custom storage structures such as tapped-delay lines, in addition to a number of very dense high-capacity Random-Access-Memory (RAM) and Content-Addressable-Memory (CAM) blocks. The extreme flexibility of the size, organization and interconnection between these storage resources enables compilers to generate custom hardware designs tailored to capture the application-specific data reuse opportunities. In this paper we outline the basic compiler data dependence analyses approaches that can be used to uncover reuse opportunities within a loop nest. We then describe the challenges of exploiting these opportunities in modern FPGAs.

Abstract
Emerging computing architectures exhibit a rich variety of controllable storage resources. Allocation and management of these resources critically affect the performance of data intensive applications. In this paper we describe a synergistic collaboration between compiler data dependence analysis and execution modeling techniques to explore the application of data caching and software prefetching for hardware designs in high-level synthesis. We describe a design space exploration algorithm that selects between data caching and prefetching of array references along the critical paths of the computation with the objective of minimizing the overall execution time, while meeting the architecture's storage and bandwidth constraints. We present preliminary results of the application of the algorithm for a set of image/signal processing kernels on a commercial FPGA. The high precision of our execution model (average 94%) results in the selection of the fastest design in every case. © 2005 IEEE.

Abstract
The purpose of this paper is to describe an adaptive algorithm for improving the performance of Bayesian Network Classifiers (BNCs) in an on-line learning framework. Instead of choosing a priori a particular model class of BNCs, our adaptive algorithm scales up the model's complexity by gradually increasing the number of allowable dependencies among features, Starting with the simple Naive Bayes structure, it uses simple decision rules based on qualitative information about the performance's dynamics to decide when it makes sense to do the next move in the spectrum of feature dependencies and to start searching for a more complex classifier. Results in conducted experiments using the class of Dependence Bayesian Classifiers on three large datasets show that our algorithm is able to select a model with the appropriate complexity for the current amount of training data, thus balancing the computational cost of updating a model with the benefits of increasing in accuracy.

Abstract
Fine-grain configurable architectures such as contemporary Field-Programmable Gate-Arrays (FPGAs) offer ample opportunities for data reuse through application-specific storage structures, making them an ideal target for memory-intensive image/signal processing computations. In this paper we explore the area and time trade-off in terms of configurable resources and overall wall-clock time of several implementation schemes that exploit opportunities for data reuse using scalar replacement in fine-grain FPGAs. The preliminary results, on a Xilinx Virtex™ FPGA device, reveal that rotation-based solutions combined with predicated accesses tend to lead to higher-quality designs. © 2005 IEEE.

Abstract
The application of ADACOR, a collaborative production automation and control architecture, is discussed. ADACOR provides a catalog of elements that simplifies the development of agent-based control systems for flexible manufacturing, from design to operation. ADACOR's Petri net-based approach facilitates the conception, definition, and formal specification of an encapsulation process in industrial production systems. ADACOR is a typical holonic/collaborative manufacturing control architecture, which addresses many of the issues defined by the ARC's Collaborative Manufacturing management (CMM) model.