1997
Autores
Barroso, J; Dagless, EL; Rafael, A; Bulas Cruz, J;
Publicação
ISIE '97 - PROCEEDINGS OF THE IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS, VOLS 1-3
Abstract
Vehicle number plate recognition systems are expected to have numerous applications in traffic surveying and monitoring, e.g. finding stolen cars, controlling access to car parks and gathering traffic flow statistics. The Computer Vision Group at the University of Tras-os-Montes e Alto Douro, in collaboration with the Universities of Aveiro and Bristol, has been developing a number plate reading system [3][4][5]. The system builds on the experience gained by the Computer Vision Group at the University of Bristol while developing previous transputer based prototypes [5][6][8][12]. The main tasks of a number plate recognition system are the location of the number plate area in the image, the segmentation of the characters and their identification. These tasks are strongly inter-related, mainly because the way to check if the number plate has been correctly located is based on the result of the character identification process (it should correspond to a predefined syntax). Algorithmic improvements to previous versions of the system, based on the results of intensive testing, are described in the paper. For the location of the number plate area in the image, a new line-based method has been developed. The method, instead of looking for character like shapes in the image, takes advantage of the "signature" of the number plate area in a horizontal cross-section of the image. The method used for the segmentation of the characters is derived from a technique first proposed by Lu [8]. The identification of the characters uses the OCR engine developed by Barroso et al [3][4], based on the critical points method [10][11].
1997
Autores
Gama, J;
Publicação
ADVANCES IN INTELLIGENT DATA ANALYSIS: REASONING ABOUT DATA
Abstract
In this paper we present system Ltree for proposicional supervised learning. Ltree is able to define decision surfaces both orthogonal and oblique to the axes defined by the attributes of the input space. This is done combining a decision tree with a linear discriminant by means of constructive induction. At each decision node Ltree defines a new instance space by insertion of new attributes that are projections of the. examples that fall at this node over the hyper-planes given by a linear discriminant function. This new instance space is propagated down through the tree. Tests based on those new attributes are oblique with respect to the original input space. Ltree is a probabilistic tree in the sense that it outputs a class probability distribution for each query example. The class probability distribution is computed at learning time, taking into account the different class distributions on the path from the root to the actual node. We have carried out experiments on sixteen benchmark datasets and compared our system with other well known decision-tree systems (orthogonal and oblique) like C4.5, OC1 and LMDT. On these datasets we have observed that our system has advantages in what concerns accuracy and tree size at statistically significant confidence levels.
1997
Autores
Torgo, L; Gama, J;
Publicação
MACHINE LEARNING : ECML-97
Abstract
We present a methodology that enables the use of classification algorithms on regression tasks. We implement this method in system RECLA that transforms a regression problem into a classification one and then uses an existent classification system to solve this new problem. The transformation consists of mapping a continuous variable into an ordinal variable by grouping its values into an appropriate set of intervals. We use misclassification costs as a means to reflect the implicit ordering among the ordinal values of the new variable. We describe a set of alternative discretization methods and, based on our experimental results, justify the need for a search-based approach to choose the best method. Our experimental results confirm the validity of our search-based approach to class discretization, and reveal the accuracy benefits of adding misclassification costs.
1997
Autores
Santos, LP; Castro, V; Proenca, A;
Publicação
RECENT ADVANCES IN PARALLEL VIRTUAL MACHINE AND MESSAGE PASSING INTERFACE
Abstract
This article presents an evaluation study of point-to-point and collective communication performance on a parallel processing system, a 16 node Parsytec PowerXplorer, using three different communication environments: PARIX, PVM and MPI.
1997
Autores
McLaughlin, AJ; Bonar, JR; Jubber, MG; Marques, PVS; Hicks, SE; Wilkinson, CDW; Aitchison, JS;
Publicação
Conference Proceedings - Lasers and Electro-Optics Society Annual Meeting-LEOS
Abstract
Flame hydrolysis deposited (FHD) silica waveguides are very important for use in planar lightwave circuits (PLC) because of their low loss and inherent compatibility with silica optical fibers. A low damage, anisotropic reactive ion etch process for the fabrication of single and multimode waveguides in silica for planar lightwave circuit applications is presented. The etch rate of the glass results in smooth sidewalls and deep anisotropic etching. Propagation losses and polarization sensitivity arising from the etch process are discussed.
1997
Autores
Alves, JC; Puga, A; CorteReal, L; Matos, JS;
Publicação
1997 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I - V: VOL I: PLENARY, EXPERT SUMMARIES, SPECIAL, AUDIO, UNDERWATER ACOUSTICS, VLSI; VOL II: SPEECH PROCESSING; VOL III: SPEECH PROCESSING, DIGITAL SIGNAL PROCESSING; VOL IV: MULTIDIMENSIONAL SIGNAL PROCESSING, NEURAL NETWORKS - VOL V: STATISTICAL SIGNAL AND ARRAY PROCESSING, APPLICATIONS
Abstract
Higher-order statistics extend the analysis methods of non-linear systems and non-gaussian signals based on the autocorrelation and power spectrum. The main drawback of their use in real time applications is the high complexity of their estimation due to the large number of arithmetic operations. This paper presents an experimental vector architecture for the estimation of the higher-order moments. The processor's core is a pipelined multiply-accumulate unit that receives four data vectors and computes in parallel the moment taps up to the fourth-order. The design of custom cache memory organization and address generation circuits has led to more than 11 operations per clock cycle. The architecture was modeled and simulated in Verilog and is presently being implemented in XILINX field-programmable gate arrays (FPGAs) and one custom integrated circuit for the multiply-accumulate unit.
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