Abstract
A soil moisture sensor (SMS) was built around RISC-like microcontroller and common peripherals to perform data acquisition, signal processing, configuration, fault-detection and data communication with a control/management system. The SMS employs capacitance and heat-pulse techniques to determine the soil water content. The sensor uses the capacitance technique as the main method while the heat-pulse readings, acquired at a lower rate, are used for calibration and fault detection purposes. The temperature sensors and the heater were assembled in a four-needle probe. Several experiments were conducted for different types of soil. The results showed that this sensor could be applied in an effective way to measure the soil water content. Several tests are being performed to conclude about the sensor dependence with soil temperature and chemical composition as well about its long-term stability.

Abstract

Abstract

Abstract
One of the most important advantages of logic programming systems is that they allow the transparent exploitation of parallelism. The different forms of parallelism available and the complex nature of logic programming applications present interesting problems to both the users and the developers of these systems. Graphical visualisation tools can give a particularly important contribution, as they are easier to understand than text based tools, and allow both for a general overview of an execution and for focusing on its important details. Towards these goals, we propose VisAll, anew tool to visualise the parallel execution of logic programs. VisAll benefits from a modular design centered in a graph that represents a parallel execution. A main graphical shell commands the different modules and presents VisAll as an unified system. Several input components, or translators, support the well-known VisAndor and VACE trace formats, plus a new format designed for independent and-parallel plus or-parallel execution in the SEA. Several output components, or visualisers, allow for different visualisations of the same execution.

Abstract
The uncertainty of project networks has been mainly considered as the randomness of duration of the activities. However, another major problem for project managers is the uncertainty due to the randomness of the amount of resources required by each activity which can be expressed by the randomness of its cost. Such randomness can seriously affect the discounted cost of the project and it may be strongly correlated with the duration of the activity. In this paper, a model considering the randomness of both the cost and the duration of each activity is introduced and the problem of project scheduling is studied in terms of the project's discounted cost and of the risk of not meeting its completion time. The adoption of the earliest (latest) starting time for each activity decreases (increases) the risk of delays but increases (decreases) the discounted cost of the project. Therefore, an optimal compromise has to be achieved. This problem of optimization is studied in terms of the probability of the duration and of the discounted cost of the project falling outside the acceptable domain (Risk function) using the concept of float factor as major decision variable. This last concept is proposed to help the manager to synthetize the large number of the decision variables representing each schedule for the studied project. Numerical results are also presented for a specific project network.

Abstract
The nesting (or placement) problem is an NP-hard combinatorial problem with important industrial applications, e.g. in apparel or footwear industry. This paper describes a hardware infrastructure to accelerate the processing of the underlying geometric information. The system consists of an FPGA-based reconfigurable platform enhanced by an ASIC for the processing of irregular polygons. The paper discusses the need for such a platform, establishes the main design guidelines and describes the architecture and modes of operation of both the reconfigurable infrastructure and the dedicated IC.