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Publicações

2003

Using depth to capture average-case complexity

Autores
Antunes, L; Fortnow, L; Vinodchandran, NV;

Publicação
FUNDAMENTALS OF COMPUTATION THEORY, PROCEEDINGS

Abstract
We give the first characterization of Turing machines that run in polynomial-time on average. We show that a Turing machine M runs in average polynomial-time if for all inputs x the Turing machine uses time exponential in the computational depth of x, where the computational depth is a measure of the amount of "useful" information in x.

2003

Sol-gel hybrid channel waveguide fabrication using UV excimer laser patterning

Autores
Moreira, PJ; Marques, PVS; Leite, AP;

Publicação
OPTICS FOR THE QUALITY OF LIFE, PTS 1 AND 2

Abstract
Definition of channel waveguides on hybrid sol-gel material was demonstrated using a 248 nm UV excimer laser. without mixing organic photoinitiators in the solution preparation step. Thin films fabricated by hydrolysis and polycondensation of methacryloxypropyltrimethoxysilane (MAPTMS) doped with zirconium oxide were deposited by spin-coating on soda-lime glass substrates (n=1.514). Channel waveguides were defined by microlithography and then covered by a protective layer composed of a combination of MAPTMS and tetramethoxysilane (TMOS). Finally, after cutting and polishing, the waveguides were optically characterised.

2003

From C programs to the configure-execute model

Autores
Cardoso, JMP; Weinhardt, M;

Publicação
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, PROCEEDINGS

Abstract
The emergence of run-time reconfigurable architectures makes feasible the configure-execute paradigm. Compilation of behavioral descriptions (in, e.g., C, Java, etc.), apart from mapping the computational structures onto the available resources on the device, must split the program in temporal sections if it needs more resources than physically available. In addition, since the execution of the computational structures in a configuration needs at least two stages (i.e., configuring and computing), it is important to split the program such that the reconfiguration overheads are minimized, taking advantage of the overlapping of the execution stages on different configurations. This paper presents mapping techniques to cope with those features. The techniques are being researched in the context of a C compiler for the eXtreme Processing Platform (XPP). Temporal partitioning is applied to furnish a set of configurations that reduces the reconfiguration overhead and thus may lead to performance gains. We also show that when applications include a sequence of loops, the use of several configurations may be more beneficial than the mapping of the entire application onto a single configuration. Preliminary results for a number of benchmarks strongly confirm the approach.

2003

Numerical methods for fiber Bragg gratings

Autores
Dionisio, RP; Lima, MJ; da Rocha, JRF; Pinto, JL; Teixeira, AJ;

Publicação
ICTON 2003: 5TH INTERNATIONAL CONFERENCE ON TRANSPARENT OPTICAL NETWORKS, VOL 2, PROCEEDINGS

Abstract
In this work several numerical methods, usually used to obtain the reflectivity spectrum of Bragg gratings, are studied and general conditions required for each method are analyzed and evidenced. The results are validated by comparison with a closed form analytical solution. For gratings where the solution is not evident, Rouard's method was used as the reference solution.

2003

Compilation for FPGA-based reconfigurable hardware

Autores
Cardoso, JMP; Neto, HC;

Publicação
IEEE DESIGN & TEST OF COMPUTERS

Abstract
These techniques for compiling software programs into reconfigurable hardware offer faster and more efficient performance than the complex resource-sharing approaches typical of high-level synthesis systems. The Java-based compiler presented in this article uses intermediate graph representations to embody parallelism at various levels.

2003

On combining temporal partitioning and sharing of functional units in compilation for reconfigurable architectures

Autores
Cardoso, JMP;

Publicação
IEEE TRANSACTIONS ON COMPUTERS

Abstract
Resource virtualization on FPGA devices, achievable due to its dynamic reconfiguration capabilities, provides an attractive solution to save silicon area. Architectural synthesis for dynamically reconfigurable FPGA-based digital systems needs to consider the case of reducing the number of temporal partitions (reconfigurations) by enabling sharing of some functional units in the same temporal partition. This paper proposes a novel algorithm for automated datapath design from behavioral input descriptions (represented by an acyclic dataflow graph), which simultaneously performs temporal partitioning and sharing of functional units. The proposed algorithm attempts to minimize both the number of temporal partitions and the execution latency of the generated solution. Temporal partitioning, resource sharing, scheduling, and a simple form of allocation and binding are all integrated in a single task. The algorithm is based on heuristics and on a new concept of construction by gradually enlarging timing slots. Results show the efficiency and effectiveness of the algorithm when compared to existent approaches.

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