Abstract

Abstract
Reconfigurable computing architectures promise to substantially increase the performance of computations through the customization of data-path and storage structures best suited to the specific needs of each computation. The need to synthesize, either fully or partially, the structure of the target architecture while simultaneously attempting to optimize the mapping of the computation to that architecture creates a vast design space exploration (DSE) challenge. In this paper we describe current approaches to this DSE problem using program analysis, estimation, modeling and empirical optimization techniques. We also describe a unified approach for this DSE challenge in which these techniques can be complemented with history- and learning-based approaches. © Springer-Verlag Berlin Heidelberg 2004.

Abstract
This work aims at developing an automatic method for the analysis of TLC images for measuring a set of features that can be used for the characterization of the distinctive patterns that result from the separation of oligosaccharides contained in human urine. This paper describes the methods developed for the automatic detection of the lanes contained in TLC images, and for the automatic separation of bands for each detected lane. The extraction of quantitative information related with each band was accomplished with two methods: the EM expectation-maximization and nonlinear least squares trust-region algorithms. The results of these methods, as well as additional quantitative information related with each band, are also presented.

Abstract

Abstract
Contemporary configurable architectures have dedicated internal functional units such as multipliers, high-capacity storage RAM, and even CAM blocks. These RAM blocks allow the implementations to cache data to be reused in the near future, thereby avoiding the latency of external memory accesses. In this paper we present a data allocation algorithm that utilizes the RAM blocks in the presence of a limited number of hardware registers. This algorithm, based on a compiler data reuse analysis, determines which data should be cached in the internal RAM blocks and when. The preliminary results, for a set of image/signal processing kernels targeting a Xilinx Virtex™ FPGA device, reveal that despite the increase latency of accessing data in RAM blocks, designs that use them require smaller configurable resources than designs that exclusively use registers, while attaining comparable and in some cases even better performance. © 2004 IEEE.

Abstract
The purpose of the research herein presented is the automatic detection of the rib borders in posterior-anterior (PA) digital chest radiographs. In a computer-aided diagnosis system, the precise location of the ribs is important as it allows reducing the false positive in the detection of abnormalities such as nodules, rib lesions and lung lesions. We adopted an edge based approach aiming at detecting the lower border of each rib. For this purpose, the rib geometric model is described as a parabola. For each rib, the upper limit is obtained using the position of the corresponding lower border.